AT25SL321 datasheet(40/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 40

Nov 1, 2022

AT25SL321 Datasheet

8.17 Block Erase (20h)

The Block Erase command is to erase the data of the selected sector as being 1. The command is used for 4K-

byte Block. Prior to the Block Erase Command, the Write Enable command must be issued. The command is

initiated by driving the CS pin low and shifting the command code 20h followed a 24-bit Block address (A23-A0).

See Figure 29 and Figure 30. The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise, the Block Erase command can not be executed. After CS goes high, the self-timed Block Erase

command commences for a time duration of tSE. See Section 9.8, AC Electrical Characteristics.

While the Block Erase cycle is in progress, the Read Status Register command can still be accessed for checking

the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is

finished and the device is ready to accept other commands again. When the BUSY bit is asserted, the Write

Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 29. Block Erase Command (SPI Mode)

Figure 30. Block Erase Command (QPI Mode)

SCK

579

829

Command

20h

24-Bit Address

Mode 3

Mode 0

Mode 3

Mode 0

MSB

SCK

2345

Mode 3

Command

A23-16

A15-8

A7-0

Mode 0

Mode 3

Mode 0

MSB

20h

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