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AT25SL321 Datasheet(PDF) 74 Page - Renesas Technology Corp |
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AT25SL321 Datasheet(HTML) 74 Page - Renesas Technology Corp |
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74 / 82 page ![]() DS-AT25SL321-112 Rev. J Page 74 Nov 1, 2022 © 2022 Renesas Electronics AT25SL321 Datasheet 1. Clock high + Clock low must be less than or equal to 1/fc. 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Contains: Read Status Register-1,2; Read Manufacturer/Device ID, Dual, Quad/ Read JEDEC ID/ Read Security Register/ Read Serial Flash Discovery Parameter. 4. Only applicable as a constraint for a Write Status Register command when Sector Protect Bit is set to 1. 9.9 Input Timing HOLD Active Hold Time relative to Clock tCHHH 5ns HOLD Not Active Setup Time relative to Clock tHHCH 5ns HOLD Not Active Hold Time relative to Clock tCHHL 5ns HOLD to Output Low-Z tHHQX 2 tLZ 7ns HOLD to Output High-Z tHLQZ 2 tHZ 12 ns Write Protect Setup Time Before CS Low tWHSL 4 20 ns Write Protect Setup Time After CS High tSHWL 4 100 ns CS High to Power Down Mode tDP 2 3µs CS High to Standby Mode without Electronic Signature Read tRES1 2 3µs c tRES2 2 1.8 µs CS High to next Command after Suspend tSUS 2 30 µs CS High to next Command after Reset tRST 2 30 µs Write Status Register Time tw 10 15 ms Byte Program Time tBP 10 150 µs Page Program Time tPP 0.6 5 ms Page Program Time (ACC = 9V) tEP 0.3 3 ms Block Erase Time (4 kB) tSE 0.06 0.4 s Block Erase Time (32 kB) tBE1 0.20 1.5 s Block Erase Time (64 kB) tBE2 0.35 2 s Chip Erase Time tCE 20 80 s 9.8 AC Electrical Characteristics (Continued) Parameter Symbol Alt Min Typ Max Units |
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