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AT25SL321 Datasheet(PDF) 44 Page - Renesas Technology Corp |
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AT25SL321 Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 82 page ![]() DS-AT25SL321-112 Rev. J Page 44 Nov 1, 2022 © 2022 Renesas Electronics AT25SL321 Datasheet 8.21 Erase / Program Suspend (75h) The Erase/Program Suspend command allows the system to interrupt a Block Erase operation or a Page Program, Quad Data Input Page Program, Quad Page Program operation. Erase Suspend is valid only during the Block erase operation. The Write Status Register-1 (01h), Write Status Register-2 (31h) command and Erase commands (20h, 52h, D8h, C7h, 60h) are not allowed during Erase Suspend. During the Chip Erase operation, the Erase Suspend command is ignored. Program Suspend is valid only during the Page Program, Quad Data Input Page Program or Quad Page Program operation. The Write Status Register-1 (01h), Write Status Register-2 (31h) command, Program commands (02h and 33h) and Erase Commands (20h, 52h, D8h, C7h, 60h) are not allowed during Program Suspend. The Erase/Program Suspend command 75h is accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend command is ignored by the device. A maximum of time of tSUS (see Section 9.8) is required to suspend the erase or program operation. After Erase/Program Suspend, the SUS bit in the Status Register is set from 0 to 1 immediately and the BUSY bit in the Status Register is cleared from 1 to 0 within tSUS. For a previously resumed Erase/Program operation, it is also required that the Suspend command 75h is not issued earlier than a minimum of time of tSUS following the preceding Resume command 7Ah. Unexpected power off during the Erase/Program suspend state resets the device and releases the suspend state. SUS bit in the Status Register is also reset to 0. The data within the page or block that was being suspended might become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. See Figure 36 and Figure 8.22. Figure 36. Erase Suspend Command (SPI Mode left, QPI Mode right) NOTE: A read operation from an 8-Mbit area (referred to as a physical block) that includes a suspended area might provide unreliable data. For the definition of the physical block and for the techniques to ensure high data integrity, see application note AN-500. SCK CS SI SO 1 0 234 6 57 Command t SUS 75h Mode 3 Mode 0 High-Impedance Mode 3 Mode 0 Accept commands SCK CS 1 0 Mode 3 Command 75h Mode 0 Mode 3 Accept commands Mode 0 t SUS IO 0 IO 1 IO 2 IO 3 |
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