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AT25SL321 Datasheet(PDF) 59 Page - Renesas Technology Corp

Part # AT25SL321
Description  32-Mbit, 1.7 V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O, and QPI Support
PDF  82 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25SL321 Datasheet(HTML) 59 Page - Renesas Technology Corp

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DS-AT25SL321-112 Rev. J
Page 59
Nov 1, 2022
© 2022 Renesas Electronics
AT25SL321 Datasheet
8.35 Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the AT25SL321 provides a software
reset command instead of a dedicated RESET pin.
Once the Reset command is accepted, any on-going internal operations are terminated and the device returns to
its default power-on state and loses all the current volatile settings, such as Volatile Status Register bits, Write
Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter
setting and Wrap bit setting.
The Enable Reset (66h) and Reset (99h) commands can be issued in either SPI mode or QPI mode. To avoid
accidental reset, both commands must be issued in sequence. Any command other than Reset (99h) after the
Enable (66h) command disables the Reset Enable state. A new sequence of Enable Reset (66h) and Reset (99h)
is needed to reset the device. Once the Reset command is accepted by the device takes approximately tRST =
30
μs to reset. During this period, no commands are accepted.
Data corruption can happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in
Status Register before issuing the Reset command sequence.
Figure 57. Enable Reset and Reset Command (SPI Mode)
Figure 58. Enable Reset and Reset Command (QPI Mode)
03
5
246
7
1
Mode 3
Mode 0
SCK
CS
Command (66h)
03
5
246
7
1
Mode 3
Mode 0
Mode 3
Mode 0
High-Impedance
Command (99h)
SI
SO
SCK
CS
1
01
0
Command
66h
Command
99h
Mode 3
Mode 0
Mode 3
Mode 0
IO
0
IO
1
IO
2
IO
3



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