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AT25SL321 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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AT25SL321 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 82 page  DS-AT25SL321-112 Rev. J Page 22 Nov 1, 2022 © 2022 Renesas Electronics AT25SL321 Datasheet 8.3 Write Enable for Volatile Status Register (50h) This command provides additional flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) command must be issued prior to a Write Status Register (01h) command. Execution of the Write Enable for Volatile Status Register command (Figure 5) does not set the Write Enable Latch (WEL) bit. Once the Write Enable for Volatile Status Register command is executed, a Write Enable command can not have been issued prior to setting Write Status Register command (01h or 31h). When the Write Enable for Volatile Status Register (50h) is set in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 must be driven to high after a Write Status Register command (01h). Once a Read Status Register (05h or 31h) is issued, the read values of SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 are ignored. Figure 5. Write Enable for Volatile Status Register Command for SPI Mode (left) and QPI Mode (right) SCK SCK CS 1 0 234 6 5 High-Impedance Command 50h 50h Mode 3 Mode 0 Mode 3 Mode 0 Mode 3 Mode 0 Mode 3 Mode 0 CS 7 1 0 SI SO IO 0 IO 1 WP IO 2 HOLD IO 3 |
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