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Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
Figure 6-3
Level 1 descriptors ............................................................................... 6-7
Figure 6-4
Section translation .............................................................................. 6-11
Figure 6-5
Page table entry, level 2 descriptor .................................................... 6-12
Figure 6-6
Small page translation ........................................................................ 6-15
Figure 6-7
Large page translation ........................................................................ 6-17
Figure 6-8
Domain access control register format ............................................... 6-21
Figure 6-9
Sequence for checking faults ............................................................. 6-22
Figure 7-1
Typical debug system........................................................................... 7-4
Figure 7-2
ARM7TDM scan chain arrangement .................................................... 7-6
Figure 7-3
Test access port (TAP) controller state transitions ............................. 7-10
Figure 7-4
ID code register format ....................................................................... 7-16
Figure 7-5
Input scan cell..................................................................................... 7-19
Figure 7-6
Clock switching on entry to debug state ............................................. 7-24
Figure 7-7
Scan general timing ............................................................................ 7-35
Figure 7-8
Reset period timing............................................................................. 7-36
Figure 7-9
Output enable and disable times due to HIGHZ TAP instruction ....... 7-36
Figure 7-10
Output enable and disable times due to data scanning...................... 7-37
Figure 8-1
ARM7TDMI TAP controller and EmbeddedICE.................................... 8-2
Figure 8-2
EmbeddedICE block diagram............................................................... 8-5
Figure 8-3
Watchpoint control value and mask format .......................................... 8-6
Figure 8-4
Debug control register format ............................................................. 8-13
Figure 8-5
Debug status register format .............................................................. 8-15
Figure 8-6
Debug control and status register structure........................................ 8-16
Figure 8-7
Debug comms control register............................................................ 8-19
Figure 9-1
Conceptual device clocking using the fastbus extension ..................... 9-3
Figure 9-2
Conceptual device clocking in standard mode ..................................... 9-5
Figure 9-3
Relationship of FCLK and BCLK in synchronous mode ....................... 9-7
Figure 10-1
Simple single-cycle access................................................................. 10-4
Figure 10-2
Simple sequential access ................................................................... 10-5
Figure 10-3
Minimum interval between bus accesses ........................................... 10-6
Figure 10-4
Use of the BWAIT pin to stop ARM720T for 1 BCLK cycle .............. 10-11
Figure 10-5
Little-endian addresses of bytes within words .................................. 10-14
Figure 10-6
Big-endian addresses of bytes within words .................................... 10-15
Figure 10-7
Bus master handover ....................................................................... 10-19
Figure 11-1
Running a test vector on the processor core ...................................... 11-2
Figure 11-2
State machine for ARM720T and ARM7TDMI test............................. 11-3
Figure 11-3
.State machine for RAM test mode..................................................... 11-6
Figure 11-4
State machine for TAG test mode ...................................................... 11-8
Figure 11-5
State machine for MMU test mode ................................................... 11-10
Figure 12-1
ETM interface signal timing ................................................................ 12-3
Figure 12-2
ETMCLK power saving ....................................................................... 12-4
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