Configuration
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
3-9
3.3.7
Register 6, Fault Address Register
Reading CP15 register 6 returns the value of the Fault Address Register (FAR). The
FAR holds the virtual address of the access that was attempted when a fault occurred.
The FAR is only updated for data faults, not for prefetch faults.
Writing CP15 register 6 sets the FAR to the value of the data written. This is useful
when a debugger has to restore the value of the FAR.
The CRm and opcode_2 fields should be zero when reading or writing CP15 register 6.
Register 6 is shown in Figure 3-10.
Figure 3-10 Register 6
Note
Register 6 contains a modified virtual address if the FCSE PID register is nonzero.
3.3.8
Register 7, cache operations
Writing to CP15 register 7 manages the unified instruction and data cache of the
ARM720T. Only one cache operation is defined using the following opcode_2 and
CRm fields in the MCR instruction that writes the CP15 register 7.
Caution
The Invalidate ID cache function invalidates all cache data. Use this with caution.
Register 7 is shown in Table 3-2.
Reading from CP15 register 7 is undefined.
3.3.9
Register 8, TLB operations
Writing to CP15 register 8 controls the Translation Lookaside Buffer (TLB). The
ARM720T implements a unified instruction and data TLB.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Fault address
Table 3-2 Cache operation
Function
opcode_2 value
CRm value
Data
Instruction
Invalidate ID cache
0b000
0b0111
SBZ
MCR
p15, 0, Rd, c7, c7, 0
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