ARM720T datasheet(55/242 Pages) ETC2

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Programmer’s Model

ARM DDI 0192A

2-19

Data Abort

This occurs during a data access.

If a Prefetch Abort occurs, the prefetched instruction is marked as invalid, but the

exception is not taken until the instruction reaches the head of the pipeline. If the

instruction is not executed, for example because a branch occurs while it is in the

pipeline, the abort does not take place.

If a Data Abort occurs, the action taken depends on the instruction type:

Single data transfer instructions (LDR, STR) write-back modified base registers,

the Abort handler must be aware of this.

The swap instruction (SWP) is aborted as though it had not been executed.

Block data transfer instructions (LDM, STM) complete. If write-back is set, the

base is updated. If the instruction attempts to overwrites the base with data (that

is, it has the base in the transfer list), the overwriting is prevented. All register

overwriting is prevented after an abort is indicated. This means, in particular,

that R15 (always the last register to be transferred) is preserved in an aborted

LDM

instruction.

After fixing the reason for the abort, the handler must execute the following irrespective

of the state (ARM or Thumb):

SUBS PC, R14_abt, #4 for a Prefetch Abort, or

SUBS PC, R14_abt, #8 for a Data Abort

This restores both the PC and the CPSR, and retries the aborted instruction.

Note

There are restrictions on the use of the external abort signal. See External aborts on

page 6-25.

2.8.7

Software interrupt

The SWI instruction is used for entering Supervisor mode, usually to request a

particular supervisor function. A SWI handler must return by executing the following

irrespective of the state (ARM or Thumb):

MOV PC, R14_svc

This restores the PC and CPSR, and returns to the instruction following the SWI.

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