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Introduction
1-6
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
1.3.2
ARM instruction set
This section gives an overview of the ARM instructions available. For full details of
these instructions, refer to the ARM Architecture Reference Manual.
The ARM instruction set formats are shown at Figure 1-2 on page 1-7.
S
Sets condition codes (optional).
B
Byte operation (optional).
H
Halfword operation (optional).
T
Forces address translation. Cannot be used with pre-indexed addresses.
<a_mode2>
Refer to Table 1-3 on page 1-11.
<a_mode2P>
Refer to Table 1-4 on page 1-12.
<a_mode3>
Refer to Table 1-5 on page 1-12.
<a_mode4L>
Refer to Table 1-6 on page 1-13.
<a_mode4S>
Refer to Table 1-7 on page 1-13.
<a_mode5>
Refer to Table 1-8 on page 1-14.
#32bit_Imm
A 32-bit constant, formed by right-rotating an 8-bit value by an even
number of bits.
<reglist>
A comma-separated list of registers, enclosed in braces ( { and } ).
Table 1-1 Key to tables (continued)
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