iv
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
2.8
Exceptions .................................................................................................. 2-16
2.9
Relocation of low virtual addresses by the FCSE PID................................ 2-22
2.10
Reset .......................................................................................................... 2-23
2.11
Implementation-defined behavior of instructions ........................................ 2-24
Chapter 3
Configuration
3.1
About configuration....................................................................................... 3-2
3.2
Internal coprocessor instructions.................................................................. 3-3
3.3
Registers ...................................................................................................... 3-4
Chapter 4
Instruction and Data Cache
4.1
About the instruction and data cache ........................................................... 4-2
4.2
IDC validity ................................................................................................... 4-4
4.3
IDC enable, disable, and reset ..................................................................... 4-5
4.4
IDC disable for secure applications .............................................................. 4-6
Chapter 5
Write Buffer
5.1
About the write buffer ................................................................................... 5-2
5.2
Write buffer operation ................................................................................... 5-3
Chapter 6
Memory Management Unit
6.1
About the MMU............................................................................................. 6-2
6.2
MMU program accessible registers .............................................................. 6-4
6.3
Address translation process ......................................................................... 6-5
6.4
Level 1 descriptor ......................................................................................... 6-7
6.5
Page table descriptor.................................................................................... 6-8
6.6
Section descriptor......................................................................................... 6-9
6.7
Translating section references ................................................................... 6-11
6.8
Level 2 descriptor ....................................................................................... 6-12
6.9
Translating small page references ............................................................. 6-14
6.10
Translating large page references.............................................................. 6-16
6.11
MMU faults and CPU aborts....................................................................... 6-18
6.12
Fault address and fault status registers...................................................... 6-19
6.13
Domain access control ............................................................................... 6-21
6.14
Fault checking sequence............................................................................ 6-22
6.15
External aborts ........................................................................................... 6-25
6.16
Interaction of the MMU, IDC, and write buffer ............................................ 6-26
Chapter 7
Debug Interface
7.1
About the debug interface ............................................................................ 7-2
7.2
Debug systems............................................................................................. 7-4
7.3
Entering debug state .................................................................................... 7-7
7.4
Scan chains and JTAG interface .................................................................. 7-9
7.5
Reset .......................................................................................................... 7-11
7.6
Public instructions....................................................................................... 7-12
7.7
Test data registers...................................................................................... 7-16
7.8
ARM7TDM core clocks............................................................................... 7-23
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
