83 / 242 page
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
6-1
Chapter 6
Memory Management Unit
This chapter describes the Memory Management Unit (MMU). It contains the following
sections:
•
About the MMU on page 6-2
•
MMU program accessible registers on page 6-4
•
Address translation process on page 6-5
•
Level 1 descriptor on page 6-7
•
Page table descriptor on page 6-8
•
Section descriptor on page 6-9
•
Translating section references on page 6-11
•
Level 2 descriptor on page 6-12
•
Translating small page references on page 6-14
•
Translating large page references on page 6-16
•
MMU faults and CPU aborts on page 6-18
•
Fault address and fault status registers on page 6-19
•
Domain access control on page 6-21
•
Fault checking sequence on page 6-22
•
External aborts on page 6-25
•
Interaction of the MMU, IDC, and write buffer on page 6-26.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
