ARM720T datasheet(91/242 Pages) ETC2

91 / 242 page

Memory Management Unit

ARM DDI 0192A

6-9

6.6

Section descriptor

Address data is described as:

C (Cachable)

Indicates that data at this address is placed in the cache if the cache

is enabled.

B (Bufferable)

Indicates that data at this address is written through the write

buffer if the write buffer is enabled.

Note

The meaning of the C and B bits might change in later ARM processors. You are

strongly recommend to structure software so that code that manipulates the MMU page

tables is contained in a single module. It can then be updated easily when you port it to

a different ARM processor.

The bits used for the page table descriptor are as follows:

Bits [3:2] (C, B)

Control the cache and write buffer related functions.

Bit [4]

Must be written to 1 for backward compatibility.

Bits [8:5]

Specify one of the 16 possible domains held in the domain access

control register that contain the primary access controls.

Bit [9]

Is always written as 0.

Bits [11:10] (AP)

Specify the access permissions for this section and are interpreted

as listed in Table 6-3 on page 6-10. Their interpretation depends

on the setting of the S and R bits, control register bits 8 and 9. The

domain access control specifies the primary access control. The

AP bits only have an effect in client mode. Refer to Domain

access control on page 6-21.

Bits [19:12]

Are always written as 0.

Bits [31:20]

Form the corresponding bits of the physical address for the 1MB

section.

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