Memory Management Unit
6-4
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
6.2
MMU program accessible registers
The ARM720T processor provides several 32-bit registers that determine the operation
of the MMU.
Data is written to and read from the MMU registers using the ARM CPU MRC and MCR
coprocessor instructions.
A brief description of the registers is given in Table 6-1. Each register is discussed in
more detail in its relevant section.
The FSR and FAR are only updated for data faults, not for prefetch faults.
Table 6-1 MMU program accessible registers
Register
Description
Translation table
base
Holds the physical address of the base of the translation table
maintained in main memory. This base must reside on a 16KB
boundary.
Domain access
control
Consists of 16 2-bit fields, each of which defines the access
permissions for one of the 16 domains (D15–D0).
TLB operations
Allows individual or all TLB entries to be marked as invalid.
Fault status
Indicates the domain and type of access being attempted when an abort
occurred.
Bits [7:4] specify which of the 16 domains (D15-D0) was being
accessed when a fault occurred.
Bits [3:1] indicate the type of access being attempted.
The encoding of these bits is different for internal and external faults
(as indicated by bit 0 in the register) and is shown in Table 6-5 on
page 6-19.
Fault address
Holds the virtual address of the access which was attempted when a
fault occurred.
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