ARM720T datasheet(7/242 Pages) ETC2

7 / 242 page

ARM DDI 0192A

vii

List of Tables

ARM720T Technical Reference Manual

Table 1-1

Key to tables ......................................................................................... 1-5

Table 1-2

ARM instruction summary ..................................................................... 1-8

Table 1-3

Addressing mode 2 ............................................................................. 1-11

Table 1-4

Addressing mode 2 (privileged) .......................................................... 1-12

Table 1-5

Addressing mode 3 ............................................................................. 1-12

Table 1-6

Addressing mode 4 (load) ................................................................... 1-13

Table 1-7

Addressing mode 4 (store).................................................................. 1-13

Table 1-8

Addressing mode 5 ............................................................................. 1-14

Table 1-9

Operand 2 ........................................................................................... 1-14

Table 1-10

Fields................................................................................................... 1-14

Table 1-11

Condition fields.................................................................................... 1-15

Table 1-12

Thumb instruction summary ............................................................... 1-17

Table 2-1

ARM720T modes of operation .............................................................. 2-7

Table 2-2

PSR mode bit values........................................................................... 2-14

Table 2-3

Exception entry and exit...................................................................... 2-17

Table 2-4

Exception vector addresses ................................................................ 2-20

Table 3-1

Cache and MMU control register .......................................................... 3-4

Table 3-2

Cache operation.................................................................................... 3-9

Table 3-3

TLB operations.................................................................................... 3-10

Table 6-1

MMU program accessible registers....................................................... 6-4

Table 6-2

Interpreting level 1 descriptor bits [1:0] ................................................. 6-7

Table 6-3

Interpreting access permission (AP) bits............................................. 6-10

Table 6-4

Interpreting page table entry bits 1:0................................................... 6-12

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