ARM720T datasheet(44/242 Pages) ETC2

44 / 242 page

Programmer’s Model

2-8

ARM DDI 0192A

2.6

Registers

ARM720T has a total of 37 registers:

•

31 general-purpose 32-bit registers

•

six status registers.

These registers cannot all be seen at once. The processor state and operating mode

dictate which registers are available to the programmer.

2.6.1

The ARM state register set

In ARM state, 16 general registers and one or two status registers are visible at any one

time. In privileged (non-User) modes, mode-specific banked registers are switched in.

Figure 2-3 on page 2-9 shows which registers are available in each mode. The banked

registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers, R0 to R15. All of

these, except R15, are general-purpose, and can be used to hold either data or address

values. In addition to these, R16 is used to store status information:

R14 is used as the subroutine link register. This receives a copy of

R15 when a Branch and Link (BL) code instruction is executed. At

all other times it can be treated as a general-purpose register. The

corresponding banked registers R14_svc, R14_irq, R14_fiq,

R14_abt, and R14_und are similarly used to hold the return values

of R15 when interrupts and exceptions arise, or when BL

instructions are executed within interrupt or exception routines.

R15 holds the Program Counter (PC). In ARM state, bits [1:0] of

R15 are zero and bits [31:2] contain the PC. In Thumb state, bit

[0] is zero and bits [31:1] contain the PC.

R16 is the Current Program Status Register (CPSR). This

contains condition code flags and the current mode bits.

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