ARM720T datasheet(67/242 Pages) ETC2

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Configuration

ARM DDI 0192A

3-7

A similar situation occurs when the MMU is disabled. The correct code sequence for

enabling and disabling the MMU is given in Interaction of the MMU, IDC, and write

buffer on page 6-26.

If the cache and write buffer are enabled when the MMU is not enabled, the results are

unpredictable.

3.3.3

Reading from CP15 register 2 returns the pointer to the currently active first-level

translation table in bits [31:14] and an unpredictable value in bits [13:0]. The CRm and

opcode_2 fields should be zero when reading CP15 register 2.

Writing to CP15 register 2 updates the pointer to the currently active first-level

translation table from the value in bits [31:14] of the written value. Bits [13:0] should

be zero. The CRm and opcode_2 fields should be zero when writing CP15 register 2.

Figure 3-6 Register 2

3.3.4

Reading from CP15 register 3 returns the value of the domain access control register.

Writing to CP15 register 3 writes the value of the domain access control register.

The domain access control register consists of 16 2-bit fields, each of which defines the

access permissions for one of the 16 domains (D15-D0).

The CRm and opcode_2 fields should be zero when reading or writing CP15 register 3.

This is shown in Figure 3-7.

Figure 3-7 Register 3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Translation base table

UNP/SBZ

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

D15 D14 D13 D12 D11 D10 D9

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