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Instruction and Data Cache
4-6
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
4.4
IDC disable for secure applications
You can disable the IDC in certain secure applications. This is achieved by forcing the
IDC to miss without triggering a line fill.
Caution
You are strongly advised not to use this feature in normal applications. When the
CACHEDIS signal is not being used then it must be held LOW.
To disable the IDC:
1.
Disable the MMU by writing to CP15 register 1 using an MCR and setting bit 0
LOW.
2.
Input the special signal, CACHEDIS.
When CACHEDIS is asserted, held HIGH, it masks out some cache signals to disable
the cache RAM banks and stop a cache hit being generated as a consequence.
Note
•
You must disable the MMU before CACHEDIS is asserted.
•
You must not enable the MMU until after CACHEDIS is deasserted.
•
ARM does not support the use of this feature.
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