ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
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List of Figures
ARM720T Technical Reference Manual
Figure 1-1
Block diagram ....................................................................................... 1-3
Figure 1-2
ARM instruction set formats .................................................................. 1-7
Figure 1-3
Thumb instruction set formats............................................................. 1-16
Figure 2-1
Big-endian addresses of bytes with words............................................ 2-3
Figure 2-2
Little-endian addresses of bytes with words ......................................... 2-4
Figure 2-3
Register organization in ARM state....................................................... 2-9
Figure 2-4
Register organization in Thumb state ................................................. 2-10
Figure 2-5
Mapping of Thumb state registers onto ARM state registers .............. 2-11
Figure 2-6
Program status register format............................................................ 2-13
Figure 3-1
MRC and MCR bit pattern..................................................................... 3-3
Figure 3-2
ID register read ..................................................................................... 3-5
Figure 3-3
ID register write ..................................................................................... 3-5
Figure 3-4
Register 1 read...................................................................................... 3-5
Figure 3-5
Register 1 write ..................................................................................... 3-5
Figure 3-6
Register 2.............................................................................................. 3-7
Figure 3-7
Register 3.............................................................................................. 3-7
Figure 3-8
Register 4.............................................................................................. 3-8
Figure 3-9
Register 5.............................................................................................. 3-8
Figure 3-10
Register 6.............................................................................................. 3-9
Figure 3-11
Register 13 with opcode_2=0 ............................................................. 3-11
Figure 3-12
Register 13 with opcode_2=1 ............................................................. 3-11
Figure 6-1
Translation table base register.............................................................. 6-5
Figure 6-2
Accessing the translation table first level descriptors............................ 6-6
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