Introduction
1-12
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
Addressing mode 2 (privileged) is listed in Table 1-4.
Addressing mode 3 is listed in Table 1-5.
Table 1-4 Addressing mode 2 (privileged)
Addressing mode 2 (privileged) <a_mode2P>
Immediate offset
[Rn, #+/-12bit_Offset]
Register offset
[Rn, +/-Rm]
Scaled register offset
[Rn, +/-Rm, LSL #5bit_shift_imm]
[Rn, +/-Rm, LSR #5bit_shift_imm]
[Rn, +/-Rm, ASR #5bit_shift_imm]
[Rn, +/-Rm, ROR #5bit_shift_imm]
[Rn, +/-Rm, RRX]
Post-indexed offset
Immediate
[Rn], #+/-12bit_Offset
Register
[Rn], +/-Rm
Scaled register
[Rn], +/-Rm, LSL #5bit_shift_imm
[Rn], +/-Rm, LSR #5bit_shift_imm
[Rn], +/-Rm, ASR #5bit_shift_imm
[Rn], +/-Rm, ROR #5bit_shift_imm
[Rn, +/-Rm, RRX]
Table 1-5 Addressing mode 3
Addressing mode 3 - signed byte, and halfword data transfer <a_mode3>
Immediate offset
[Rn, #+/-8bit_Offset]
Pre-indexed
[Rn, #+/-8bit_Offset]!
Post-indexed
[Rn], #+/-8bit_Offset
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