SC28L202 datasheet(43/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

Modification of the IVR

Bits 7:3

Bits 2:1

Bit 0

Always contains bits (7:3) of the IVR

Will be replaced with current interrupt

type if IVC field of GCCR = 3

Replaced with interrupting channel

number if IVC field of GCCR > 1

The table above indicates how the IVR may be modified by the interrupting source. The modification of the IVR as it is presented to the data bus

during an IACK cycle is controlled by the setting of the bits (2:1) in the GCCR (Global Chip Configuration Register).

GICR – Global Interrupting Channel Register

Bits 7:1

Bit 0

Reserved

Channel code

0 = a

1 = b

A register associated with the interrupting channel as defined in the CIR. It contains the channel number for the interrupting channel.

GIBCR – Global Interrupting Byte Count Register

Bits 7:0

Channel byte count code

00000001 = 1

00000010 = 2

11111111 = 255

00000000 = 256

A register associated with the interrupting channel as defined in the

CIR. Its numerical value equals TxEL or RxFL at the time IACKN or

“Update CIR” command was issued . The true number of bytes

ready for transfer to the transmitter or transfer from the receiver. It is

undefined for other types of interrupts

GITR – Global Interrupting Type Register

Bit 7:6

Bit 5

Bit 4:3

Bit 2:0

Receiver Interrupt

Transmitter Interrupt

Reserved

Other types

0x = not receiver

10 = with receive errors

11 = w/o receive errors

0 = not transmitter

1 = transmitter interrupt

read 0x00

000 = not ”other” type

001 = Change of State

010 = Address Recognition Event

011 = Xon/Xoff status

100 = Rx Watchdog

101 = Break Change

110 = Counter Timer

111 = Rx Loop Back Error

A register associated with the interrupting channel as defined in the CIR. It contains the type of interrupt code for all interrupts.

GRxFIFO – Global RxFIFO Register

Bits 7:0

8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data

The RxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a receiver interrupt.

Global

TxFIFO Register

GTxFIFO – Global TxFIFO Register

Bits 7:0

8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data

The TxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a transmitter interrupt. Writing to

the GTxFIFO when the current interrupt is not a transmitter event may result in the characters being transmitted on a different channel than

intended.

BCRBRK – Bidding Control Register – Break Change, A and B

Bits 7:0

MSBs of break change interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for a break change interrupt.

BCRCOS – Bidding Control Register – Change of State, A and B

Bits 7:0

MSBs of Change of state detectors (COS) interrupt bid

This register provides the 8 MSBs of the Interrupt Arbitration number for a Change of State, COS, interrupt.

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