SC28L202 datasheet(45/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

I/OPCR 0 – I/O Port Configuration Register

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

I/O3 A control

I/O2 A control

I/O1 A control

I/O0 A control

00 = GPI / TxC A

01 = OPR[3] A

10 = TxC A (16X) Output

11 = Reserved

00 = GPI / CT 0 Clock Input

01 = OPR[2] A / DTRN A

10 = TxC A (1X) Output

11 = Reserved

00 = GPI / CTSN B

01 = OPR[1] A

10 –

11 = Reserved

00 = GPI / CTSN A

01 = OPR[0] A

10 –

11 = Reserved

I/OPCR 1 – I/O Port Configuration Register

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

I/O7 A control

I/O6 A control

I/O5 A control

I/O4 A control

00 = GPI / CT 1 Clock Input

01 = OPR[7] A / DTRN B

10 = TxC B (1X) Output

11 = Reserved

00 = GPI / RxC B / PBRG 1 Clk Input

01 = OPR[6] A

10 = RxC B (16X) Output

11 = Reserved

00 = GPI / TxC B

01 = OPR[5] A

10 = TxC B (16X) Output

11 = Reserved

00 = GPI / RxC A / PBRG 0 Clk Input

01 = OPR[4] A

10 = RxC A (16X) Output

11 = Reserved

I/OPCR 2 – I/O Port Configuration Register

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

I/O3 B control

I/O2 B control

I/O1 B control

I/O0 B control

00 = GPI /DSRN B

01 = OPR[3] B

10 = RxC B (1X) Output

11 = C/T 0 Output (open

drain)

00 = GPI /DSRN A

01 = OPR[2] B

10 = RxC A (1X) Output

11 = C/T 1 Output (open drain)

00 = GPI

01 = OPR[1] B / RTSN B

10 = Reserved

11 = Reserved

00 = GPI

01 = OPR[0] B / RTSN B

10 = Reserved

11 = Reserved

I/OPCR 3 – I/O Port Configuration Register

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

I/O7 B control

I/O6 B control

I/O5 B control

I/O4 B control

00 = GPI /RIN B

01 = OPR[7] B

10 =TxINTN B (open drain)

11 =reserved

00 = GPI /RIN A

01 = OPR[6] B

10 =TxINTN A (open drain)

11 = reserved

00 = GPI /DCDN B

01 = OPR[5] B

10 = RxINTN B (open

drain)

11 = reserved

00 = GPI /DCDN A

01 = OPR[4] B

10 = RxINTN A (open drain)

11 = reversed

NOTE: Both I/O Port A and B default to input upon a hardware reset to avoid hardware conflicts with I/O direction

The four registers above contain 4, 2 bit fields that set the direction and source for each of the I/O pins associated with the channel. The I/O0 B

or I/O1 B output may be RTSN if MR1[7] is set. It may also signal ”end of transmission” if MR2[5] is set. (Please see the descriptions of these

functions under the MR1 and MR2 register descriptions).

The binary settings of the binary 00 combination always configures the I/O pins as “inputs”. However the input circuit of the I/O pins are

ALWAYS active. In actuality the binary 00 condition only disable the output driver of the pin. Since the input circuit and the associated change of

state detector is always active the output signal may generate interrupts or drive counters.

This register resets to 0x00 on reset, effectively configuring all I/O pins as inputs. Inputs may be used as RxC, TxC inputs or CTSN and General

Purpose Inputs simultaneously. All inputs are equipped with change detectors that may be used to generate interrupts or can be polled, as

required.

SOPR A and SOPR B – Set the Output Port Bits (OPR A and OPR B)

SOPR [7:0] – Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This

allows software to set individual bits with our keeping a copy of the OPR bit configuration. One register for each channel.

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Set OPR Bits

OPR 7

OPR 6

OPR 5

OPR 4

OPR 3

OPR 2

OPR 1

OPR 0

1=set bit

0=no

change

1=set bit

0=no

change

1=set bit

0=no

change

1=set bit

0=no change

1=set bit

0=no change

1=set bit

0=no change

1=set bit

0=no change

1=set bit

0=no

change

SC28L202 Datasheet(PDF) 45 Page - NXP Semiconductors

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