SC28L202 datasheet(28/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

UART Registers

These registers are generally concerned with formatting,

transmitting and receiving data.

The user must exercise caution when changing the mode of running

receivers, transmitters, PBRG or counter/timers. The selected mode

will be activated immediately upon selection, even if this occurs

during the reception or transmission of a character. It is also

possible to disrupt internal controllers by changing modes at critical

times, thus rendering later transmission or reception faulty or

impossible.

An exception to this policy is switching from auto–echo or remote

loop back modes to normal mode. If the deselecting occurs just after

the receiver has sampled the stop bit (in most cases indicated by

the assertion of the channel’s RxRDY bit) and the transmitter is

enabled, the transmitter will remain in auto–echo mode until the end

of the transmission of the stop bit.

MR0 – Mode Register 0, A and B

MR0 can be accessed directly at H’20” and H’28” in the Extended section of the address map, or by means of the “MR Pointers” at the 0x00

and 0x08 address pointers used by legacy code.

(TEST 1)

(TEST 3)

Bit 7

BIT 6

BIT (5:4)

BIT 3

BIT 2

BIT 1

BIT 0

MR0 A, MR0

B, and

MR0 B[3:0]

are reserved

Rx Watchdog

0 = Disable

1 = Enable

RxINT BIT 2

See Tables in

MR0

description

TxINT (1:0)

See Table 13

FIFO Size

0 = 8 bytes

1 = 256

bytes

BAUD RATE

EXTENDED II

0 = NormaL

1 = Extend II

Reserved

Set to 0

BAUD RATE

EXTENDED 1

0 = Normal

1 = Extend

*This bit control is duplicated at MR0[7].

MR0[7] Fixed length Watchdog Timer

This bit controls the receiver watchdog timer. 0 = disable, 1 =

enable. When enabled, the watch dog timer will generate a receiver

interrupt if the receiver FIFO has not been accessed within 64 bit

times of the receiver 1X clock. This is used to alert the control

processor that data is in the RxFIFO that has not been read. This

situation may occur when the byte count of the last part of a

message is not large enough to generate an interrupt.

MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit

6 of MR1 sets the fill level of the 8 byte FIFO that generates the

receiver interrupt.

MR0[6] and MR1[6] Note that this control is split between MR0 and

MR1. This is for backward compatibility to the SC2692 and

SCN2681.

Table 3. Receiver FIFO Interrupt Fill Level

MR0(3)=0

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (RxRDY)

3 or more bytes in FIFO

6 or more bytes in FIFO

8 bytes in FIFO (Rx FULL)

Table 4. Receiver FIFO Interrupt Fill Level

MR0(3)=1

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (RxRDY)

128 or more bytes in FIFO

192 or more bytes in FIFO

256 bytes in FIFO (Rx FULL)

For the receiver these bits control the number of FIFO positions

filled when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

MR0[5:4] – Tx interrupt fill level.

Table 5. Transmitter FIFO Interrupt Fill Level

MR0(3)=0

MR0[5:4]

Interrupt Condition

8 bytes empty (Tx EMPTY)

4 or more bytes empty

6 or more bytes empty

1 or more bytes empty (TxRDY)

Table 6. Transmitter FIFO Interrupt Fill Level

MR0(3)=0

MR0[5:4]

Interrupt Condition

256 bytes empty (Tx EMPTY)

128 or more bytes empty

192 or more bytes empty

1 or more bytes empty (TxRDY)

For the transmitter these bits control the number of FIFO positions

empty when the receiver will attempt to interrupt. After the reset the

transmit FIFO has 8 bytes empty. It will then attempt to interrupt as

soon as the transmitter is enabled. The default setting of the MR0

bits (00) condition the transmitter to attempt to interrupt only when it

is completely empty. As soon as one byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

MR0[3] – FIFO Size

Selects between 8 or 256 byte FIFO structure

MR0[2:0] – Legacy Baud Rate Group Selection

These bits are used to select one of the six–baud rate groups.

See Table 13 for the group organization.

• 000 Normal mode

• 001 Extended mode I

• 100 Extended mode II

Other combinations of MR2[2:0] should not be used

NOTE: MR0[3:0] are not used in channel B and should be set to 0.

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