SC28L202 datasheet(14/77 Pages) PHILIPS

14 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

up to three characters. The recognition is done on a byte boundary

and sets status and interrupt when recognition events occur. Three

modes of automatic operation are provided for the in–band flow

control and three modes of automatic operation are provided for

address recognition. Both in–band flow control and address

recognition may also be completely under the control of the host

processor.

A subset of the recognition system is Xon/Xoff character recognition

and the recognition of the multi–drop address character. If Xon/Xoff

or multi–dorp function is enabled the recognition system passes the

information about the recognition event to the appropriate receiver

or transmitter state machine for execution. In any case the

information about a recognition event is available to the interrupt

system and to the control processor.

Flow Control

Flow control is implemented in either the traditional RTS/CTS

protocol or in the “inbound” Xon/Xoff method. Both may be

controlled by fully/partially automatic methods or by interrupt

generation.

Test Modes and Software

Four test modes are provided to verify UART function and processor

interface integrity. The first three are Auto echo, Local Loop Back,

and Remote Loop Back. Through local loop back the software

developer may verify all of the interrupt, flow control; the hardware

designer verify all of the timing and pin connections. This information

is obtained without any recourse to external test equipment, logic

analyzers or terminals.

The fourth, Receiver Error Loop back verification, employs a method

of automatic checking (accounting for transmission delays) of the

transmitted data to as echoed back through the remote receiver.

Errors generate interrupt and status events.

DETAILED DESCRIPTIONS

NOTE: For the convenience of the reader some paragraphs

of the following sections are repeated in descriptions of

closely linked functions described in other sections.

Bus Interface

The bus interface operates in two modes selected by the I/M pin. If

this pin is high or left open the signals DACKN signal is not

generated or used and data flow to and from the chip is controlled

by the state the CEN, RDN, WRN pin combination. If the I/M pin is

tied low the data is written to the device when the DACKN pin is

asserted low by the DUART. Read data is presented by a delay from

CEN active.

The Host interface is comprised of the signal pins CEN, WRN RDN,

(or R/WN) IACKN, DACKN, IRQN, 6 address pins and 8 three–state

data bus pins. Addressing of the various functions of the DUART is

through the address bus A(6:0). Data is presented on the 8–bit data

bus.

DACKN Cycle

When operating in the “68K” mode bus cycle completion is indicated

by the DACKN pin (an open drain signal) going low. The timing of

DACKN is by GCCR(6) where two time delays area available. The

delay begins with the falling edge of CEN and DACKN is presented

after either two edges of he X1/Sclk (1/2 X1/Sclk Cycle) or, under

program control, a short internal delay of less than 50 ns. Usually in

this mode the address and data are set up with respect to the

leading edges of the bus cycle.

The DACKN pin is a three state driver. At the termination of an

access to the L202 a very short pulse (less than 5 ns) drives the pin

high and immediately returns to the high impedance state. This will

occur at the termination of the CEN or IACKN cycle.

NOTE: The faster X86 timing may be used in the 68K mode IF the

bus cycles are faster than 1/2 period of the Sclk clock. Withdrawing

CEN before DACKN prevents the generation of DACKN. In this case

bus timing is effectively that of the X86 mode.

When operating in the “x86” mode DACKN is not generated. Data is

written on the termination of CEN or WRN whichever one occurs

first. Read data is presented from the leading edge of the read

condition (CEN and RDN both low).

IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert

the IACKN signal low. This will cause the intelligent interrupt system

of the DUART to generate an IACKN cycle in which the condition of

the interrupting source is determined. When IACKN asserts, the last

valid of the interrupt arbitration cycle is captured in the CIR. The

value captured presents all of the important details of the highest

priority interrupt at the moment the IACKN (or the ”Update CIR”

command) was asserted. Due to system interrupt latency the

interrupt condition captured by the CIR may not be the condition that

caused the initial assertion of the interrupt.

The Dual UART will respond to the IACKN cycle with an interrupt

vector. The interrupt vector may be a fixed value, the content of the

Interrupt Vector Register, or when ”Interrupt Vector Modification” is

enabled via ICR, it may contain codes for the interrupt type and/or

interrupting channel. This allows the interrupt vector to steer the

interrupt service directly to the proper service routine. The interrupt

value captured in the CIR remains until another IACKN or “Update

CIR” command is given to the DUART. The interrupting channel and

interrupt type fields of the CIR set the current ”interrupt context” of

the DUART. The channel component of the interrupt context allows

the use of Global Interrupt Information registers that appear at fixed

positions in the register address map. For example, a read of the

Global RxFIFO will read the channel B RxFIFO if the CIR interrupt

context is channel B receiver. At another time read of the GRxFIFO

may read the channel A RxFIFO (CIR holds a channel A receiver

interrupt) and so on. Global registers exist to facilitate qualifying the

interrupt parameters and for writing to and reading from FIFOs

without explicitly addressing them.

The CIR will load with 0x00 if IACKN or Update CIR is asserted

when the arbitration circuit is NOT asserting an interrupt. In this

condition there is no arbitration value that exceeds the threshold

value. When Interrupt vector modification is active in this situation

the interrupt vector bits associated with the CIR will all be zero. A

zero type field indicates nothing with in the DUART is requiring

processor service.

NOTE: IACKN is essentially a special read action where the value of

the interrupt vector is presented to the data bus.

Timing Circuit

Crystal Oscillator

The crystal oscillator operates directly from a crystal, tuned between

7.0 MHz and 16.2 MHz connected across the X1/Sclk and X2 inputs

with a minimum of external components. BRG values listed for the

clock select registers correspond to a 14.7456 MHz crystal

frequency. Use of different frequencies will change the “standard”

baud rates by precisely the ratio of 14.7456 MHz to the different

crystal frequency.

An external clock up to 50 MHz frequency range may be connected

to X1/Sclk pin. If an external clock is used instead of a crystal,

X1/Sclk must be driven and X2 left floating or driving a load of not

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