SC28L202 datasheet(57/77 Pages) PHILIPS

57 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

The registers of the SC28L202 are LOOSELY partitioned into two

groups: those used in controlling data channels and those used in

handling the actual data flow and status. Below is shown the general

configuration of all the register addressed. The ”Register Map

Summary” shows the configuration of the lower four bits of the

address that is the same for THE INDIVIDUAL UARTs. It also shows

the addresses for the several in the address space of UART A and

UART B that apply to the total chip configuration. The ”Register Map

Detail” shows the use of every address in the 8–bit address space.

NOTE: The register maps for channels A and B (UARTs A and B)

contain some control registers that configure the entire chip. These

are denoted by a ”” symbol

Addressing Scheme:

³ B+8

Default

³ Extension

+16

NOTE: Addresses 0x00 to 0x0F represent the “C92 Register” map

A(6:0)

READ

WRITE

DEFAULT

000 0000 (0x00)

Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT

000 0001 (0x01)

Status Register (SR A)

Clock Select Register (CSR A) DEFAULT

000 0010 (0x02)

Command Register (CR A) DEFAULT

000 0011 (0x03)

Receiver FIFO Register (RxFIFO A)

Transmitter FIFO Register (TxFIFO A)

000 0100 (0x04)

• Input Port Change Register (IPCR) DEFAULT

• Auxiliary Control Register (ACR) DEFAULT

000 0101 (0x05)

• Interrupt Status Register (ISR) DEFAULT

• Interrupt Mask Register (IMR) DEFAULT

000 0110 (0x06)

• Counter Timer Value Register Upper (CTVU 0)

• Counter Timer Preset Register Upper (CTPU 0)

000 0111 (0x07)

• Counter Timer Value Register Lower (CTVL 0)

• Counter Timer Preset Register Lower (CTPL 0)

000 1000 (0x08)

Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT

000 1001 (0x09)

Status Register (SR B)

Clock Select Register (CSR B) DEFAULT

000 1010 (0x0A)

Command Register (CR B) DEFAULT

000 1011 (0x0B)

Receiver FIFO Register (RxFIFO B)

Transmitter FIFO Register (TxFIFO B)

000 1100 (0x0C)

• Interrupt Vector Register (IVR) GLOBAL

000 1101 (0x0D)

• Input Port Register (IPR) I/O(6:0) A

• Output Port Configuration Register (OPCR) I/O(7:2)B

000 1110 (0x0E)

• Start Counter Command DEFAULT C/T 0

• Set Output Port Register (SOPR) I/O(7:0)B

000 1111 (0x0F)

• Stop Counter Command DEFAULT C/T 0

• Reset Output Port Register (ROPR) I/O(7:0)B

EXTENSION

001 0000 (0x10)

Receiver FIFO Fill Level (RxFL A)

• Set Output Port Register (SOPR A)

001 0001 (0x11)

Transmitter FIFO Empty level (TxEL A)

• Reset Output Port Register (ROPR A)

001 0010 (0x12)

• Enhanced Operation Status (EOS)

Command Register Extension (CRx A)

001 0011 (0x13)

• Input Port Change Register Upper (IPCRU A)

• I/O Port Configuration Register 0 (I/OPCR 0)

001 0100 (0x14)

• Input Port Change Register Lower (IPCRL A)

• I/O Port Configuration Register 1 (I/OPCR 1)

001 0101 (0x15)

• Input Port Register (IPR A)

001 0110 (0x16)

• Counter Timer Value Register Upper (CTVU 0)

• Counter Timer Preset Register Upper (CTPU 0)

001 0111 (0x17)

• Counter Timer Value Register Lower (CTVL 0)

• Counter Timer Preset Register Lower (CTPL 0)

001 1000 (0x18)

Receiver FIFO Fill Level (RxFL B)

• Set Output Port Register (SOPR B)

001 1001 (0x19)

Transmitter FIFO Empty level (TxEL B)

• Reset Output Port Register (ROPR B)

001 1010 (0x1A)

Command Register Extension (CRx B)

001 1011 (0x1B)

• Input Port Change Register Upper (IPCRU B)

• I/O Port Configuration Register 2 (I/OPCR 2)

001 1100 (0x1C)

• Input Port Change Register Lower (IPCRL B)

• I/O Port Configuration Register 3 (I/OPCR 3)

001 1101 (0x1D)

• Input Port Register (IPR B)

001 1110 (0x1E)

• Counter Timer Value Register Upper (CTVU 1)

• Counter Timer Preset Register Upper (CTPU 1)

001 1111 (0x1F)

• Counter Timer Value Register Lower (CTVL 1)

• Counter Timer Preset Register Lower (CTPL 1)

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