SC28L202 datasheet(55/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

CTVL Counter –Timer Value Lower (Counter/Timer 0)

CTVL

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

The lower eight (8) bits for the 16 bit counter timer value register

Only the counter/timer 0 is available in the low order 16–position

address map. Issuing the start command loads the C/T with the

preset value. The Stop command resets the C/T ready bit in the ISR

(Interrupt status Register) and captures the C/T value in the output

latches of the C/T. In the special time out mode the start and stop

commands are ignored. The “start command is executed by a read

at address 0xE; the stop at 0xF.

IVR Interrupt Vector register in 68K mode and General purpose read write register in the x86 mode

IVR

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

The eight (8) bits of the interrupt vector in the 68K mode.

IPR Input Port Register I/O(6:0) A

IPR

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Logical levels or the I/O[6:0] A, Bit 7 read as “1”

OPCR Output Port Configuration Register. Controls [7:2] B

Bit 7

BIT 6

BIT 5

BIT 4

BIT (3:2)

BIT (1:0)

I/O7 B

I/O6 B

I/O5 B

I/O4 B

I/O3 B

I/O2 B

0 = OPR[7]

1 = Tx RDY B

0 = OPR[6]

1 = Tx RDY A

0 = OPR[5]

1 = Rx RDY / FFULL B

0 = OPR[4]

1 = Rx RDY / FFULL A

00 = OPR[3]

01 = C/T OUTPUT

10 = TxC B(1X)

11 = RxC B(1X)

00 = OPR[2]

01 = TxC A(16X)

10 = TxC A(1X)

11 = RxC A(1X)

NOTE: I/O0 B and I/O1 B output OPR(0) and OPR(1) respectively.

Under program control of MR1 and MR2 the signals RTSN A for

I/O0 B and RTSN B for I/O1 B may be assigned.

OPCR[7] –This bit programs the I/O7 B output to provide one of the

following:

• 0 The complement of OPR[7].

• 1 The Channel B transmitter interrupt output which is the

complement of ISR[4]. When in this mode I/O7 acts as an open–

drain output. Note that this output is not masked by the contents

of the IMR.

OPCR[6] –This bit programs the I/O6 B output to provide one of the

following:

• 0 The complement of OPR[6].

• 1 The Channel A transmitter interrupt output which is the

complement of ISR[0]. When in this mode I/O6 acts as an open–

drain output. Note that this output is not masked by the contents

of the IMR.

OPCR[5] –This bit programs the I/O5 B output to provide one of the

following:

• 0 The complement of OPR[5].

• 1 The Channel B receiver interrupt output which is the

complement of ISR[5]. When in this mode I/O5 acts as an

open–drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[4] –This field programs the I/O4 B output to provide one of

the following:

• 0 The complement of OPR[4].

• 1 The Channel A receiver interrupt output which is the

complement of ISR[1]. When in this mode I/O4 acts as an

open–drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[3:2] –This bit programs the I/O3 B output to provide one of

the following:

• 00 The complement of OPR[3].

• 01 The counter/timer output, in which case I/O3 acts as an

open–drain output. In the timer mode, this output is a square wave

at the programmed frequency. In the counter mode, the output

remains high until terminal count is reached, at which time it goes

low. The output returns to the high state when the counter is

stopped by a stop counter command. Note that this output is not

masked by the contents of the IMR.

• 10 The 1X clock for the Channel B transmitter that shifts the

transmitted data. If data is not being transmitted, a free running 1X

clock is output.

• 11 The 1X clock for the Channel B receiver that samples the

received data. If data is not being received, a free running 1X

clock is output.

OPCR[1:0] –This field programs the I/O2 B output to provide one of

the following:

• 00 The complement of OPR[2].

• 01 The 16X clock for the Channel A transmitter. This is the clock

selected by CSR A [3:0], and will be a 1X clock if CSR A [3:0] =

1111.

• 10 The 1X clock for the Channel A transmitter that shifts the

transmitted data. If data is not being transmitted, a free running 1X

clock is output.

• 11 The 1X clock for the Channel A receiver that samples the

received data. If data is not being received, a free running 1X

clock is output.

SC28L202 Datasheet(PDF) 55 Page - NXP Semiconductors

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