SC28L202 datasheet(52/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

CR Command Register

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CR A &CR B

MISCELLANEOUS COMMANDS

Disable Tx

Enable Tx

Disable Rx

Enable Rx

See Text of Channel Command Register

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.

COMMAND REGISTER TABLE A and B

Commands 0xE, 0xF (marked with *) are global and exist only in channel A’s register space.

Channel Command Code

Channel Command

Channel Command Code

Channel Command

CR[7:4]

Description

CR[7:4]

Description

0000

NOP

1000

Assert RTSN (I/O0 B or I/O1 B)

0001

Set MR pointer to 1

1001

Negate RTSN (I/O0 B or I/O1 B)

0010

Reset Receiver

1010

Set C/T Receiver time–out mode on

0011

Reset Transmitter

1011

Set MR pointer to 0

0100

Reset Error Status

1100

Set C/T Receiver time–out mode off

0101

Reset Break Change Interrupt

1101

Block Error Status on RxFIFO load

0110

Begin Transmit Break

1110

• Power Down Mode On

0111

End Transmit Break

1111

• Disable Power Down Mode

• 0000 No command.

• 0001 set MR pointer to 1

• 0010 Reset receiver. Immediately resets the receiver as if

hardware reset had been applied. The receiver is reset and the

FIFO pointer is reset to the first location effectively discarding all

unread characters in the FIFO.

• 0011 Reset transmitter. Immediately resets the transmitter as if a

hardware reset had been applied. The transmitter is reset and the

FIFO pointer is reset to the first location effectively discarding all

untransmitted characters in the FIFO.

• 0100 Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]). I

It is used in either character or block mode. In block mode it would

normally be used after the block is read.

• 0101 Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be cleared to

zero.

• 0110 Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active and the

TxFIFO is empty then the break begins when transmission of the

current character is completed. If there are characters in the

TxFIFO, the start of break is delayed until all characters presently

in the TxFIFO and any subsequent characters loaded have been

transmitted. (Tx Idle must be true before break begins).

The transmitter must be enabled to start a break.

• 0111 Stop break. The TxD line will go high (marking) within two bit

times. TxD will remain high for one bit time before the next

character is transmitted.

• 1000 Assert RTSN. Causes the RTSN output to be asserted (low).

• 1001 Negate RTSN. Causes the RTSN output to be negated

(high).

NOTE: The two commands above actually reset and set,

respectively, the I/O0 B or I/O1 B pin associated WITH the

OPR register.

• 1010 Set C/T Receiver time out mode on. The receiver in this

channel will restart the C/T as reach receive character is

transferred from the shift register to the RxFIFO. The C/T is

placed in the Counter Mode, the Start/Stop Counter commands

are disabled, the counter is stopped and the Counter Ready bit,

ISR(3), is reset.

• 1011 Set MR Pointer to 0

• 1100 Set C/T Receiver time out mode off

• 1101 Block error status accumulation on FIFO entry. Allows the

“received break”, “framing error” and “parity error” bits to be set as

the received character is loaded to the RxFIFO. (normally these

bits are set on reading of the data from the RxFIFO) Setting this

mode can give information about error data up to 256 bytes earlier

than the normal mode. However it clouds the ability to know

precisely which byte(s) are in error.

• 1110 Power Down Mode On

• 1111 Disable Power Down Mode

SC28L202 Datasheet(PDF) 52 Page - NXP Semiconductors

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