SC28L202 datasheet(53/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

IPCR Input Port Configuration Register

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IPCR

Delta

I/O 3A

Delta

I/O 2A

Delta

I/O 1A

Delta

I/O 0A

I/O 3A

I/O 2A

I/O 1A

I/O 0A

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

0 = no change

1 = change

0 = low

1 = High

0 = low

1 = High

0 = low

1 = High

0 = low

1 = High

IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change–of–State

These bits are set when a change–of–state, as defined in the input

port section of this data sheet, occurs at the respective input pins.

They are cleared when the IPCR is read by the CPU. A read of the

IPCR also clears ISR [7], the input change bit in the interrupt status

an interrupt to the CPU.

IPCR [3:0] I/O3 A, I/O2 A, I/O1 A, I/O0 A logical level of I/O pin.

These bits provide the current state of the respective inputs. The

information is unlatched and reflects the state of the input pins at the

time the IPCR is read.

ACR Auxiliary Control Register

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ACR

BRG SET

Select

Counter Timer Mode

and

clock source select

Delta

I/O3 A interrupt

enable

Delta

I/O2 A interrupt

enable

Delta

I/O1 A interrupt

enable

Delta

I/O0 A interrupt

enable

0 = set 1

1 = set 2

See Table 14

0 = off

1 = enabled

0 = off

1 = enabled

0 = off

1 = enabled

0 = off

1 = enabled

ACR[7] – Baud Rate Generator Set Select

This bit selects one of two sets of baud rates to be generated by the

BRG and it effects both channels. (see Table 13).

ACR[6:4] – Counter/Timer Mode And Clock Source Select

This field selects the operating mode of the counter/timer and its

clock source as shown in Table 14.

ACR [3:0] – I/O3 A, I/O2 A, I/O1 A, I/O0 A Change–of–State

Interrupt Enable

This field selects which bits of the input port change register (IPCR)

cause the input change bit in the interrupt status register (ISR [7]) to

be set. If a bit is in the ‘on’ state the setting of the corresponding bit

in the IPCR will also result in the setting of ISR [7], which results in

the generation of an interrupt output if IMR [7] = 1. If a bit is in the

‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].

Table 14. ACR 6:4 Field Definition

ACR(6:4)

MODE

CLOCK SOURCE

000

Counter

External (I/02A)

001

Counter

TxC A – 1X clock of Channel A

transmitter

010

Counter

TxC B – 1X clock of Channel B

transmitter

011

Counter

(X1/Sclk) clock divided by 16

100

Timer

External (I/O 2A)

101

Timer

External (I/O2 A) divided by 16

110

Timer

Crystal or external clock (X1/Sclk)

111

Timer

(X1/Sclk) clock divided by 16

NOTE: The timer mode generates a square wave.

SC28L202 Datasheet(PDF) 53 Page - NXP Semiconductors

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