SC28L202 datasheet(15/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

more than 2 CMOS or TTL equivalents. The X1/Sclk clock serves as

the basic timing reference for the baud rate generator (BRG) and is

available to the programmable BRG (PBRG), counter–timers,

control logic and the UART receivers and transmitters.

Baud Rate Generator BRG

The baud rate generator operates from the oscillator or external

X1/Sclk clock input and generates 27 commonly used data

communications baud rates (including MIDDI) ranging from 50 to

921.6K baud. These common rates may be increased (up to 3000K

baud) when faster clocks are used on the X1/Sclk clock input. (See

Receiver and Transmitter Clock Select Register descriptions.) All of

these are available simultaneously for use by any receiver or

transmitter. The clock outputs from the BRG are at 16X the actual

baud rate.

Please see counter timer description for a description of the

frequency error that the asynchronous protocol may tolerate.

Depending on character length it varies from 4.1% to 6.7%.

Counter–Timer

The two Counter/Timers are programmable 16 bit dividers that are

used for generating miscellaneous clocks or generating timeout

periods. These clocks may be used by any or all of the receivers

and transmitters in the DUART or may be directed to an I/O pin for

miscellaneous use.

Counter/Timer programming

The counter timer is a 16–bit programmable divider that operates in

one of four modes: character count, counter, timer, and time out.

Character count counts characters. The timer mode generates a

square wave. In the counter mode it generates a time delay. In the

time out mode it monitors the time between received characters.

The C/T uses the numbers loaded into the Counter/Timer Lower

its divisor. The counter timer is controlled with six commands:

Start/Stop C/T, Read/Write Counter/Timer lower register and

Read/Write Counter/Timer upper register. These commands have

slight differences depending on the mode of operation. Please see

the detail of the commands under the CTPL/CTPU Register

descriptions.

Whenever the these timers are selected via the receiver or

transmitter Clock Select register their output will be configured as a

16x clock for the respective receiver or transmitter. Therefore one

needs to program the timers to generate a clock 16 times faster than

the data rate. The formula for calculating ’n’, the number loaded to

the CTPU and CTPL registers, based on a particular input clock

frequency is shown below.

For the timer mode the formula is as follows:

Clockinputfrequency

(Baud rate desired))

NOTE: ‘n’ may assume a value of 1. In previous Philips data

communications controllers this value was not allowed. The

Counter/Timer Clock Select Register (CTCS) controls the

Counter/Timer input frequency.

The frequency generated from the above formula will be at a rate 16

times faster than the desired baud rate. The transmitter and receiver

state machines include divide by 16 circuits, which provide the final

frequency and provide various timing edges used in the qualifying

the serial data bit stream. Often this division will result in a

non–integer value: 26.3 for example. One may only program integer

numbers to a digital divider. There for 26 would be chosen. If 26.7

were the result of the division then 27 would be chosen. This gives a

baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error

of 1.14% or 1.12% respectively, well within the ability of the

asynchronous mode of operation. Higher input frequency to the

counter reduces the error effect of the fractional division

One should be cautious about the assumed benign effects of small

errors since the other receiver or transmitter with which one is

communicating may also have a small error in the precise baud rate.

In a ”clean” communications environment using one start bit, eight

data bits and one stop bit the total difference allowed between the

transmitter and receiver frequency is approximately 4.6%. Less than

eight data bits will increase this percentage.

Programmable Baud Rate Generators. PBRG

Two PBRG Counters (Used only for random baud rate generation)

The two PBRG Timers are programmable 16 bit dividers that are

used for generating miscellaneous clocks. These clocks may be

used by any or all of the receivers and transmitters in the SC28L202

or output to the general purpose I/O pins.

Each timer unit has eight different clock sources available to it as

described in the PBRG clock source Register. Note that the timer

run and stop controls are also contained in this register. The PBRG

counters generate a symmetrical square wave whose half period is

equal in time to the division of the selected PBRG Timer clock

source by the number loaded to the PBRGPU and PBRGPL Preset

Registers. Thus, the output frequency will be the clock source

frequency divided by twice the 16 bit value loaded to these registers.

This is the result of counting down once for the high portion of the

output wave and once for the low portion.

Whenever the these timers are selected via the receiver or

transmitter Clock Select register their output will be configured as a

16x clock for the respective receiver or transmitter. Therefore one

needs to program the timers to generate a clock 16 times faster than

the data rate. The formula for calculating ’n’, the number loaded to

the PBRGPL and PBRGPU registers, is the same as shown above

I/O Ports

Eight I/O ports are “loosely” provided for each channel. They may be

programmed to be inputs or outputs. The input circuits are always

active whether programmed as and input or an output. In general a

2–bit code in the

I/OPCR (I/O Port Control Register) controls what

function these pins will present. All I/O ports default to high

impedance input state on power up.

When calling software written for previous Philips (Signetics)

DUARTs the user should be sure to declare I/O ports to be

inputs where drivers may be attached to an I/O port pin that

previous software had expected to be an output.

Input Characteristics of the I/O ports

Eight I/O pins are provided for each channel. These pins are

configured individually to be inputs or outputs. As inputs they may

be used to bring external data to the bus, as clocks for internal

functions or external control signals. Each I/O pin has a ”Change of

State” detector. The change detectors are used to signal a change in

the signal level at the pin (Either 0 to 1 or 1 to 0 transitions). The

level change on these pins must be stable for 25 to 50 us (two

edges of the 38.4 KHz baud rate clock) before the detectors will

signal a valid change. These are typically used for interface signals

from modems to the DUART and from there to the host.

Output Port of the I/O ports

The OPR, I/OPCR, MR, and CR registers may control the I/O pins

when configured as outputs. (For the control in the loser 16 position

address space the control register is the OPCR) Via appropriate

programming the pins of the output port may be configures as

another parallel port to external circuits, or they may represent

internal conditions of the UART. When this 8–bit port is used as a

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