SC28L202 datasheet(35/77 Pages) PHILIPS

35 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

SR – Channel Status Register A and B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Received Break

Framing Error

Parity Error

Overrun Error

Tx Idle

TxRDY

RxFULL

RxRDY

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

SR[7] – Received Break

This bit indicates that an all zero character (including parity, if used)

of the programmed length has been received with a stop bit at a

logical zero. A single FIFO position is loaded with 0x00 when a

break is received; further entries to the FIFO are inhibited until the

RxD line returns to the marking state for at least one half bit time

(two successive edges of the internal or external 1x clock). When

this bit is set, the change in break bit in the ISR (ISR [2]) is set.

ISR[2] is also set when the end of the break condition, as defined

above, is detected. The break detect circuitry is capable of detecting

breaks that originate in the middle of a received character. However,

if a break begins in the middle of a character, it must last until the

end of the next character in order for it to be detected.

SR[6] – Framing Error (FE)

This bit indicates that a stop bit was not detected when an otherwise

non–zeros data character (including parity, if enabled) was received.

The stop bit check is made in the middle of the first stop bit position.

SR[5] – Parity Error (PE)

This bit is set when the ’with parity’ or ’force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In the special ’wake up mode’, the

parity error bit stores the received A/D bit.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of the

start bit of a new character when the RxFIFO is full and a character

is already in the receive shift register (257 valid characters in the

receiver) waiting for an empty FIFO position. When this occurs, the

character in the receive shift register (and its break detect, parity

error and framing error status, if any) is lost. This bit is cleared by a

reset error status command.

SR [3] – Transmitter Idle (Tx Idle)

This bit is set when the transmitter underruns, i.e., both the TxFIFO

and the transmit shift register are empty. It is set after transmission

of the last stop bit of a character, if no character is in the TxFIFO

awaiting transmission. It is negated when the TxFIFO is loaded by

the CPU, or when the transmitter is disabled or reset. This bit is

concerned with the transmitter transmitting data and it essentially

shows “ transmitter underrun”. If, while it is underrun it is

commanded to send an X on/Xoff character it will remain at the zero

state. If it is underrun and while sending an Xon/Xoff character the

TxFIFO is loaded then the bit will go low.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded

with at least one more character. This bit is cleared when the

TxFIFO is full or is above its interrupt threshold level set in the MR

registers or TxFIFO interrupt Fill Level register (TxFIL). Characters

loaded in the TxFIFO while the transmitter is disabled will not be

transmitted.

SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift

become full, i.e., all 256 RxFIFO positions are occupied. It is reset

when the CPU reads the RxFIFO and that read leaves one or more

empty byte position(s). If a character is waiting in the receive shift

second read of the RxFIFO since the waiting character is

immediately loaded to the RxFIFO.

SR[0] – Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the RxFIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the RxFIFO and reset

when the CPU reads the RxFIFO, and no more characters are in the

RxFIFO.

SC28L202 Datasheet(PDF) 35 Page - NXP Semiconductors

SC28L202 Datasheet(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL