SC28L202 datasheet(37/77 Pages) PHILIPS

37 / 77 page

Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

IMR – Interrupt Mask Register A and B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I/O Port Change of state

Rx Watch–dog

Time–out

Address

recognition event

Xon/off

event

C/T

Ready

Break Change

Of State

RxRDY

interrupt

TxRDY

interrupt

The programming of this register selects which bits in the ISR cause

an interrupt output. If a bit in the ISR is a ’1’ and the corresponding

bit in the IMR is a ’1’, the interrupt source is presented to the internal

interrupt arbitration circuits, eventually resulting in the IRQN output

being asserted (low). If the corresponding bit in the IMR is a zero,

the state of the bit in the ISR has no affect on the IRQN output.

IMR[7] COS enable

Allows a change of state in the inputs equipped with input change

detectors to cause an interrupt.

IMR[6] Fixed Watchdog Enable

Controls the generation of an interrupt watchdog timer event. If set,

a count of 64 idle bit times in the receiver will begin interrupt

arbitration.

IMR[5] Address recognition enable

Enables the generation of an interrupt in response to changes in the

Address Recognition circuitry of the Special Mode (multi–drop or

wake–up mode).

IMR[4] Xon/Xoff Enable

Enables the generation of an interrupt in response to recognition of

an in–band flow control character.

IMR[3] Counter/Timer Enable

Enable the C/T interrupt when the C/T reaches 0 count.[2] Enables

the generation of an interrupt when a Break condition has been

detected by the channel receiver.

IMR[1] Receiver (Rx) Enable

Enables the generation of an interrupt when servicing for the

RxFIFO is desired.

IMR[0] Transmitter (Tx) Enable

Enables the generation of an interrupt when servicing for the

TxFIFO is desired.

RxFIFO – Receiver FIFO, A and B

Bit[10]

Bit[9]

Bit[8]

Bits [7:0]

These bits are sent to the status register

This the data byte sent to the data bus or RxFIFO read

Break

Received Status

Framing

Error Status

Parity

Error Status

8 data bits

MSBs =0 for 7,6,5 bit data

The FIFO for the receiver is 11 bits wide and 256 ”words” deep. The

status of each byte received is stored with that byte and is moved

along with the byte as the characters are read from the FIFO. The

upper three bits are presented in the STATUS register and they

change in the status register each time a data byte is read from the

FIFO. Therefor the status register should be read BEFORE the byte

is read from the RxFIFO if one wishes to ascertain the quality of the

byte

The foregoing applies to the ”character error” mode of status

reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block

error” status reporting. Briefly, ”Block Error” gives the accumulated

error of all bytes received by the RxFIFO since the last “Reset Error”

command was issued. (CR = 0x04)

TxFIFO – Transmitter FIFO, A and B

Bits 7:0

8 data bits. MSBs set to 0 for 7, 6, 5 bit data

The FIFO for the transmitter is 8 bits wide by 256 bytes deep. For character lengths less than 8 bits the upper bits will be ignored by the

transmitter state machine and thus are effectively discarded.

RxFIL – Receiver FIFO Interrupt Level, A and B

Bits 7:0

Any one of 256 FIFO fill positions

The position in the Rx FIFO that causes the receiver will enter the interrupt arbitration process. This register is used to offset the effect of the

arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also “equalize” interrupt latency and allow for larger

aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.

RxFL – Receiver FIFO Fill Level Register

Bits 7:0

Channel byte count code ** (1) = implied ‘1’

00000001 = 1

00000010 = 2

11111111 = 255

**(1)00000000 = 256 if RxRDY status bit is set.

The number of bytes filled in the receiver FIFO

SC28L202 Datasheet(PDF) 37 Page - NXP Semiconductors

SC28L202 Datasheet(HTML) 37 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL