SC28L202 datasheet(51/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

CSR A – Channel A Clock Select Register CSR A [7:4] –

Channel A Receiver Clock Select

This field selects the baud rate clock for the Channel A receiver. The

field definition is shown in Table 13.

CSR Clock Select Register

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CSR A & CSR B

RECEIVER CLOCK SELECT

TRANSMITTER CLOCK SELECT

See Text and Table 13

Table 13. Baud Rate (Base on a 14.7456 MHz crystal clock)

MR0[0] = 0 (Normal Mode)

MR0[0] = 1 (Extended Mode I)

MR0[2] = 1 (Extended Mode II)

CSR A [7:4]

ACR[7] = 0

ACR[7] = 1

ACR[7] = 0

ACR[7] = 1

ACR[7] = 0

ACR[7] = 1

0000

300

450

4,800

7,200

0001

110

880

0010

134.5

1,076

0011

200

150

1200

900

19.2K

14.4K

0100

300

1800

28.8K

0101

600

3600

57.6K

0110

1,200

7200

7,200

115.2K

0111

1,050

2,000

1,050

2,000

1,050

2,000

1000

2,400

14.4K

57.6K

1001

4,800

28.8K

4,800

1010

7,200

1,800

7,200

1,800

57.6K

14.4K

1011

9,600

57.6K

9,600

1100

38.4K

19.2K

230.4K

115.2K

38.4K

19.2K

1101

Timer

1110

I/O4 A–16X

1111

I/O4 A–1X

NOTE: The receiver clock is always a 16X clock except for CSR A [7:4] = 1111.

CSR A [3:0] – Channel A EXTERNAL Transmitter Clock Select

This field selects the baud rate clock for the Channel A transmitter.

The field definition is as shown in Table 13, except as follows:

CSR A [3:0]

ACR[7] = 0

ACR[7] = 1

1110

I/O3 A–16X

1111

I/O3 A–1X

The transmitter clock is always a 16X clock except for CSR[3:0] =

1111.

CSR B [7:4] – Channel B Receiver Clock Select

This field selects the baud rate clock for the Channel B receiver. The

field definition is as shown in Table 13, except as follows:

CSR B [7:4]

ACR[7] = 0

ACR[7] = 1

1110

I/O6 A–16X

111

I/O6 A–1X

The receiver clock is always a 16X clock except for CSR B [7:4] =

1111.

CSR B [3:0] – Channel B Transmitter Clock Select

This field selects the baud rate clock for the Channel B transmitter.

The field definition is as shown in Table 13, except as follows:

CSR B [3:0]

ACR[7] = 0

ACR[7] = 1

1110

I/O5 A–16X

1111

I/O5 A–1X

The transmitter clock is always a 16X clock except for CSR B [3:0] =

1111.

Rx FIFO Register. For characters shorter than 8 bits the unused bits are set to zero

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Bits of the received data characters.

Tx FIFO register. For characters shorter than 8 bits the unused bits are set to zero

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Bits of the data characters to be transmitted

CR A and B Command Register

CR, one for each channel, controls the channel commands and

enables/disables the receiver and transmitter. Commands may be to

the upper and lower four bits in the same bus cycle. If both enable

and disable bits are set to 1 in the lower four bits a disable will

result.

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