SC28L202 datasheet(38/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

TxFIL – Transmitter FIFO Interrupt Level A and B

Bits 7:0

Any one of 256 FIFO empty positions

The position in the Tx FIFO that caused the transmitter will enter the interrupt arbitration process. This register is used to offset the effect of the

arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also “equalize” interrupt latency and allow for larger

aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.

TxEL – Transmitter FIFO Empty Level Register

Bits 7:0

Channel byte count code ** (1) = implied ‘1’

00000001 = 1

00000010 = 2

11111111 = 255

**(1)00000000 = 256 if TxRDY status bit is set.

The number of empty bytes in the Transmitter FIFO

Registers for Character Recognition

XonCR – Xon/Xoff Character Register A and B

Bits 7:0

8 Bits of the Xon Character Recognition (Resets to 0x11)

An 8–bit character register that contains the compare value for a Xon character.

XoffCR – Xoff Character Register A and B

Bits 7:0

8 Bits of the Xoff Character Recognition (Resets to 0x13)

An 8–bit character register that contains the compare value for a Xoff character.

ARCR – Address Recognition Character Register A and B

Bits 7:0

8 Bits of the Multi–Drop Address Character Recognition (Resets to 0x00)

An 8 bit character register that contains the compare value for the wake–up address character

SC28L202 Datasheet(PDF) 38 Page - NXP Semiconductors

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