PM3350-SW datasheet(24/224 Pages) PMC

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ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

PCI Expansion Bus Interface

Signal Name

Size

Type

Description

AD[31:0]

I/O

Multiplexed PCI address/data bus, used by an external bus master (e.g., a PCI

host) or the ELAN 8x10 to transfer addresses or data.

CBE_[3:0]

I/O

Command/Byte-Enable lines. These lines supply a command (during PCI address

phases) or byte enables (during data phases) for each bus transaction.

PAR

I/O

Address/data/command parity, supplies the even parity computed over the

AD[31:0] and CBE_[3:0] lines during valid data phases; it is sampled (when the

ELAN 8x10 is acting as a target) or driven (when the ELAN 8x10 acts as an

initiator) one clock edge after the respective data phase.

FRAME_

I/O

Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this signal

indicates that a new transaction is beginning (with an address phase); a LOW-to-

HIGH transition indicates that the next valid data phase will end the currently

ongoing transaction.

IRDY_

I/O

Transaction Initiator (master) ready, used by the transaction initiator or bus master

to indicate that it is ready for a data transfer. A valid data phase ends with data

transfer when both IRDY_ and TRDY_ are sampled asserted on the same clock

edge.

TRDY_

I/O

Transaction Target ready, used by the transaction target or bus slave to indicate

that it is ready for a data transfer. A valid data phase ends with data transfer when

both IRDY_ and TRDY_ are sampled asserted on the same clock edge.

STOP_

I/O

Transaction termination request, driven by the current target or slave to abort,

disconnect or retry the current transfer.

DEVSEL_

I/O

Device select acknowledge: driven by a target to indicate to the initiator that the

address placed on the AD[31:0] lines (together with the command on the

CBE_[3:0] lines) has been decoded and accepted as a valid reference to the

target's address space. Once asserted, it is held asserted until FRAME_ is

de-asserted; otherwise, it indicates (in conjunction with STOP_ and TRDY_) a

target-abort.

IDSEL

Device identification (slot) select. Assertion of IDSEL signals the ELAN 8x10 that it

is being selected for a configuration space access.

REQ_

Bus request (to bus arbiter), asserted by the ELAN 8x10 to request control of the

PCI bus.

GNT_

Bus grant (from bus arbiter); this indicates to the ELAN 8x10 that it has been

granted control of the PCI bus, and may begin driving the address/data and control

lines after the current transaction has ended (indicated by FRAME_, IRDY_ and

TRDY_ all de-asserted simultaneously).

INT_

Open Drain Interrupt request. This pin signals an interrupt request to an external

PCI host system. The INT

_ pin should be tied to the INTA* line on the PCI bus.

PERR_

I/O

Bus parity error signal, asserted by the ELAN 8x10 as a bus slave, or sampled by

the ELAN 8x10 as a bus master, to indicate a parity error on the AD[31:0] and

CBE_[3:0] lines.

SERR_

Open Drain System error, used by the ELAN 8x10 to indicate a system error, or a

parity error on the AD[31:0] and CBE_[3:0] lines during an address phase.

PCI_CLK

PCI bus clock; supplies the PCI bus clock signal to the ELAN 8x10.

PM3350-SW Datasheet(PDF) 24 Page - PMC-Sierra, Inc

PM3350-SW Datasheet(HTML) 24 Page - PMC-Sierra, Inc

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