PM3350-SW datasheet(59/224 Pages) PMC

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ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

MDATA[29]

RSTTM

For test purposes only. Pull low for correct operation.

MDATA[28]

IMDIS

Internal memory disable: if high, the internal Switch Processor

ROM is disabled at initialization time.

MDATA[27]

PCI3V

If high, configures the PCI interface for the 3.3V signaling

environment. If low, configures the PCI interface for the 5V

signaling environment.

Must be set to logic 0 since all AC

parametric testing done with the 5V signaling conditions.

MDATA[26]

FIRM

Reserved for use by Switch Processor firmware.

MDATA[25:22]

CHIPID[3:0]

These bits determine the PCI memory base address at

initialization time if the PCIRUN configuration bit is high. In this

case, the CHIPID[3:0] inputs are zero-extended to 8 bits and

loaded into the most significant byte of the Memory Base

Address register in the PCI configuration register space.

MDATA[21:16]

RTCDIV[5:0]

Real time clock divider: selects the divide ratio used for the

internal real-time clock prescaler. This field must be set

numerically equal to the frequency, in megahertz, of the clock

supplied on the SYSCLK input.

MDATA[15:14]

MXSEL[1:0]

These inputs select the row/column multiplexing used for EDO

DRAM devices.

MXSEL

Column

Address Bits

DRAM Configurations

Supported

64K x N & 128K x N

256K x N & 512K x N

1024K x N & 2048K x N

4 Meg x N & 8 Meg x N

MDATA[13]

MSLO

The MSLO bit extends read and write cycles to accommodate

slower local memory devices. If MSLO is high, memory

accesses will be to 80ns DRAM. If MSLO is low, 60ns DRAM is

expected. The PM3350 is intended to be used with 60ns EDO

DRAM; hence, MSLO must be a logic 0. The access time for

ROM is always 150ns, respectively, regardless of the state of the

MSLO bit.

MDATA[12]

MDCAS

This bit identifies the type of DRAM connected to the

memory interface. If MDCAS is high, the memory interface

will generate control signals for 2-CAS DRAMs; otherwise,

it generates signals for single CAS DRAMs.

MDATA[11:9]

MTYPE3[2:0]

Indicates the type of memory connected to the MCS[3]* output:

MTYPE3[2:0]

000

001

010

011

100

101

110

111

Selected memory type

Reserved

200ns (E)EPROM

60ns EDO DRAM

Reserved

MDATA[8:6]

MTYPE2[2:0]

Indicates the memory type associated with MCS[2]*. The

encoding is the same as for MTYPE3[2:0].

PM3350-SW Datasheet(PDF) 59 Page - PMC-Sierra, Inc

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