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PM3350-SW Datasheet(PDF) 28 Page - PMC-Sierra, Inc |
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PM3350-SW Datasheet(HTML) 28 Page - PMC-Sierra, Inc |
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28 / 224 page ![]() ELAN 8X10 PM3350 ELAN 8 X10 DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY 26 Miscellaneous Inputs and Outputs Signal Name Size Type Description VDD5 1 I The 5 volt bias pin must be connected to 5.0 volts for the input and bi-directional pins to be 5 volt tolerant. This pin may be tied to VDD provided the maximum static signal level is below VDD + 0.3V. During power-up, the voltage on the VDD5 pin must be kept equal to or greater then the voltage on all input pins to avoid damage to the device. In addition, the voltage on the VDD5 pin is to be kept greater than or equal to the voltage on the VDD pins. TST_ 1 I Test select signal used for production testing. It must be tied high for correct operation. ERST_ 1 OD Open-drain external reset output. The ERST_ pin is driven low by the ELAN 8x10 to reset other components in the system. This output is asserted for a pre- set duration (10 milliseconds) upon the detection of a falling edge on the RST_ input, or when the ELAN 8x10 senses a condition requiring a system hardware reset. It is an open-drain output, and should be pulled up using a 2.2k resistor. The ERST_ output may be tied directly to the RST_ input to implement a debounce function in pushbutton reset applications. (Note that the ERST_ output should be left unconnected in host-based applications where the ELAN 8x10 must not be allowed to reset the host CPU.) DBG[2:0] 3 I/O PMC hardware debug pins. These pins are used for hardware debug and should not be used. These pins should be implemented as no-connects. PC[10:3] 8 O PMC hardware debug pins. Program counter selected outputs. These pins are used for hardware debug and should not be used. These pins should be implemented as no-connects. Notes on Pin Description: 1. All inputs and bi-directionals present minimal capacitive loading and operate at TTL logic levels. 2. All digital outputs and bi-directionals have 2 mA D.C. drive capability. 3. Pins MDATA[31:0], MINTR_,RST_, GNT_, TST_ and DBG[2:0] have internal pull- up resistors. |
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