PM3350-SW datasheet(55/224 Pages) PMC

55 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

retried transaction to the address from which it began the prefetch; if a match occurs,

the slave logic will return the data present in the read FIFO in a continuous burst of

back-to-back data phases on the PCI bus. The burst of transfers on the PCI bus will

continue as long as (1) the read FIFO is not empty and (2) the bus master does not

terminate the access.

If the read FIFO empties during a transfer (possibly because the memory controller

cannot satisfy the requests from the PCI slave logic at a sufficient rate), the PCI slave

logic will issue another disconnect with retry, and continue to request the memory

controller for more data. The bus master is again expected to retry the access, and the

cycle continues.

If the bus master terminates the access in any way, the PCI slave logic will stop placing

data on the PCI bus and flush the read FIFO to discard any remaining unread data

words. It will then proceed to fulfill the next PCI read or write access.

The use of the PCI slave read FIFO enhances the ability of the PCI slave logic to

maintain the utilization of the PCI bus by transferring data in long bursts. If sufficient

delay is inserted by the bus master between the initial disconnected access and the

subsequent retry, the PCI slave will have time to read ahead by a substantial number of

words (up to 32) and can therefore transfer data in a long burst when the bus master

finally retries the access.

To further improve the efficiency of the PCI slave interface, the slave logic has the

capability of latching and holding up to two different target read addresses from two

different bus masters at a time. This allows the first bus master to make a read access,

which will be disconnected with retry by the PCI slave logic after the target address has

been latched; another bus master can then make another read access at a different

address, which will also be disconnected with retry by the slave logic after the address

has been latched. (Only two such addresses can be latched by the slave; if yet a third

master makes another read access to another address, the slave logic will also

disconnect this master with a retry, but will not latch the address internally.) The

availability of the second read address means that the PCI slave logic can begin

immediately fetching data from the second location into the read FIFO after the first bus

master terminates its access, without waiting for the second bus master to retry the

access, and hence the PCI slave logic can improve its utilization of the available

memory and PCI bus bandwidth.

Note:

Writes are not allowed to be completed out-of-sequence with reads, and vice

versa.

PM3350-SW Datasheet(PDF) 55 Page - PMC-Sierra, Inc

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