PM7347 datasheet(268/341 Pages) PMC

268 / 341 page

S/UNI®-JET Data Sheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

268

Document ID: PMC-1990267, Issue 3

The processing of the overhead bits in the DS3 frame is described in Table 38. In the transmit

direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream

using the TOH, TOHINS, TOHFP, and TOHCLK signals. In the receive direction, most of the

overhead bits our brought out serially on the ROH data stream.

Table 38 DS3 Frame Overhead Operation

Control Bit

Transmit Operation

Receive Operation

Xx:

X-Bit Channel

Inserts the FERF signal on the

X-bits.

Monitors and detects changes in the state of

the FERF signal on the X-bits.

Px:

P-Bit Channel

Calculates the parity for the

payload data over the previous

M-frame and inserts it into the

P1 and P2 bit positions.

Calculates the parity for the received payload.

Errors are accumulated in internal registers.

Mx:

M-Frame Alignment

Signal

Generates the M-frame

alignment signal (M1=0, M2=1,

M3=0).

Finds the M-frame alignment by searching for

the F-bits and the M-bits. OOF is removed if

the M-bits are correct for three consecutive M-

frames while no discrepancies have occurred

in the F-bits.

Fx:

M-subframe

Alignment Signal

Generates the M-subframe

signal (F1=1, F2=0, F3=0,

F4=1).

Finds M-frame alignment by searching for the

F-bits and the M-bits. OOF is removed if the

M-bits are correct for three consecutive M-

frames while no discrepancies have occurred

in the F-bits.

Cx:

C-Bit Channels

M23 Operation:

The C bits are passed through

transparently in M23 framer only

mode except for the C-bit Parity

ID bit which toggles every M-

frame. In M23 ATM applications,

the C bits other than the Parity

ID bit are forced to logic one.

C-bit Parity Operation:

The C-bit Parity ID bit is forced to

logic one. The second C-bit in M-

subframe 1 is set to logic one.

The third C-bit in M-subframe 1

provides a far-end alarm and

control (FEAC) signal. The FEAC

channel is sourced by the XBOC

block. The 3 C-bits in M-

subframe 3 carry path parity

information. The value of these 3

C-bits is the same as that of the

P-bits. The 3 C-bits in M-

subframe 4 are the FEBE bits.

The 3 C-bits in M-subframe 5

contain the 28.2 Kbit/s path

maintenance datalink. The

remaining C-bits are unused and

set to logic one.

The state of the C-bit parity ID bit is stored in a

C-bit parity format is received.

C-bit Parity Operation:

The FEAC channel on the third C-bit in M-

subframe 1 is detected by the RBOC block.

Path parity errors and FEBEs on the C-bits in

M-subframes 3 and 4 are accumulated in

counters. The path maintenance datalink

signal is extracted by the receive HDLC

controller.

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