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PM7347 Datasheet(PDF) 311 Page - PMC-Sierra, Inc

Part # PM7347
Description  SATURN USER NETWORK INTERFACE for J2/E3/T3
PDF  341 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7347 Datasheet(HTML) 311 Page - PMC-Sierra, Inc

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S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
311
Document ID: PMC-1990267, Issue 3
Figure 57 Framer Mode DS3 Transmit Input Stream
TDATI
INFO 84
TFPI/TMFPI
INFO 84
INFO 83
INFO 82
X1
INFO 2
INFO 1
X2
INFO 1INFO 2INFO 3
INFO 84
INFO 82 INFO 83
F4
INFO 82 INFO 83
TFPO/TMFPO
TICLK
Figure 58 Framer Mode DS3 Transmit Input Stream With TGAPCLK
TGAPCLK
TDATI
INFO 1
INFO 83
INFO 82
INFO 81
INFO 3
INFO 2
INFO 2
INFO 3
INFO 4
INFO 1
INFO 83 INFO 84
INFO 83
INFO 84
TICLK
INFO 1
The Framer Mode DS3 Transmit Input Stream diagrams (Figure 57 and Figure 58) show the
expected format of the inputs TDATI and TFPI/TMFPI along with TICLK and the output
TFPO/TMFPO when the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set, and
the S/UNI-JET is configured for the DS3 transmit format. If the TXMFPI register bit is logic
zero, then TFPI is valid, and the S/UNI-JET will expect TFPI to pulse for every DS3 overhead bit
with alignment to TDATI. If the TXMFPI register bit is logic one, then TMFPI is valid, and the
S/UNI-JET will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the
TXMFPO register bit is logic zero, then TFPO is valid, and the S/UNI-JET will pulse TFPO once
every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If
the TXMFPO register bit is logic one, then TMFPO is valid and the S/UNI-JET will pulse
TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-
frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between
TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO
when the TXGAPEN bit in the S/UNI-JET Configuration 2 Register is set to logic one, as in
Figure 58. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the
falling edge of TGAPCLK.
Figure 59 Framer Mode DS3 Receive Output Stream
RDATO
INFO 84
RFPO/RMFPO
INFO 84
INFO 83
INFO 82
X1
INFO 2
INFO 1
X2
INFO 1INFO 2INFO 3
INFO 84
INFO 82
INFO 83
F4
INFO 82
INFO 83
ROVRHD
RSCLK]



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