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PM7347 Datasheet(PDF) 312 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 312 Page - PMC-Sierra, Inc |
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312 / 341 page ![]() S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 312 Document ID: PMC-1990267, Issue 3 Figure 60 Framer Mode DS3 Receive Output Stream with RGAPCLK RGAPCLK RDATO INFO 84 INFO 84 INFO 83 INFO 82 INFO 2 INFO 1 INFO 1 INFO 2 INFO 3 INFO 84 INFO 82 INFO 83 INFO 82 INFO 83 INFO 84 The Framer Mode DS3 Receive Output Stream diagrams (Figure 59 and Figure 60) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set. Figure 59 shows the data streams when the S/UNI-JET is configured for the DS3 receive format. If the RXMFPO and 8KREFO register bits are logic zero, RFPO is valid and will pulse high for one RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register bit is a logic one (as shown in Figure 59) and the 8KREFO register bit is logic zero, RMFPO is valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. As shown in Figure 60 the RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-JET Configuration 2 Register is set to logic one. RGAPCLK remains high during the overhead bit positions and RDATO does not change. Figure 61 Framer Mode G.751 E3 Transmit Input Stream TDATI bit 1536 0 TFPI/TMFPI Nat RAI 11 1 10 1 0 0 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 TFPO/TMFPO 0 bit13 TICLK Figure 62 Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK TGAPCLK TDATI bit 1536 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 bit14 TICLK bit13 |
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