PM7347 datasheet(313/341 Pages) PMC

313 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

313

Document ID: PMC-1990267, Issue 3

The Framer Mode G.751 E3 Transmit Input Stream diagrams (Figure 61 and Figure 62) show the

expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO

(and TGAPCLK) when the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set,

and the S/UNI-JET is configured for the E3 G.751 transmit format. TFPI or TMFPI pulses high

for one TICLK cycle and is aligned to the first bit of the frame alignment signal in the G.751 E3

input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 1536 TICLK

cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or

TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The

TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the S/UNI-

JET Configuration 2 Register is set to logic one, as in Figure 62. TGAPCLK remains high during

the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK.

Figure 63 Framer Mode G.751 E3 Receive Output Stream

RDATO

bit 1536

RFPO/RMFPO

Nat

RAI

bit 1531

bit 1529

bit 1530

bit 1532 bit 1533 bit 1534

bit 1535

ROVRHD

bit13

RSCLK

Figure 64 Framer Mode G.751 E3 Receive Output Stream with RGAPCLK

RGAPCLK

RDATO

bit 1536

bit 1531

bit 1529

bit 1530

bit 1532

bit 1533

bit 1534

bit 1535

bit13

The Framer Mode G.751 E3 Receive Output Stream diagrams (Figure 63 and Figure 64) show the

format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when

the FRMRONLY and the 8KREFO bits in the S/UNI-JET Configuration 1 Register are set to

logic one and logic zero respectively. Figure 63 shows the data streams when the S/UNI-JET is

configured for the E3 G.751 receive format. RFPO or RMFPO pulses high for one RSCLK cycle

and is aligned to the first bit of the framing alignment signal in the G.751 E3 output data stream

on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. If

the PYLD&JUST register bit in the E3 FRMR Maintenance Options Register is set to logic zero,

the Cjk and Pk bits in the RDATO stream will be marked as overhead bits. If the PYLD&JUST

payload. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the

S/UNI-JET Configuration 2 Register is set to logic one. RGAPCLK remains high during the

overhead bit positions as shown in Figure 64.

PM7347 Datasheet(PDF) 313 Page - PMC-Sierra, Inc

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