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PM7347 Datasheet(PDF) 115 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 115 Page - PMC-Sierra, Inc |
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115 / 341 page  S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 115 Document ID: PMC-1990267, Issue 3 Register 311H: PMON Interrupt Enable/Status Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 R/W INTE 0 Bit 1 R INTR X Bit 0 R OVR X OVR The OVR bit indicates the overrun status of the PMON holding registers. A logic one in this bit position indicates that a previous interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have been overwritten. A logic zero indicates that no overrun has occurred. This bit is reset to logic zero when this register is read. INTR The INTR bit indicates the current status of the interrupt signal. A logic one in this bit position indicates that a transfer of counter values to the holding registers has occurred; a logic zero indicates that no transfer has occurred. The INTR bit is set to logic zero when this register is read. INTE The INTE bit enables the generation of an interrupt when the PMON counter values are transferred to the holding registers. When a logic one is written to INTE, the interrupt generation is enabled. |
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