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PM7347 Datasheet(PDF) 118 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 118 Page - PMC-Sierra, Inc |
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118 / 341 page  S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 118 Document ID: PMC-1990267, Issue 3 Register 318H: PMON Excessive Zero Count LSB Bit Type Function Default Bit 7 R EXZS[7] X Bit 6 R EXZS[6] X Bit 5 R EXZS[5] X Bit 4 R EXZS[4] X Bit 3 R EXZS[3] X Bit 2 R EXZS[2] X Bit 1 R EXZS[1] X Bit 0 R EXZS[0] X Register 319H: PMON Excessive Zero Count MSB Bit Type Function Default Bit 7 R EXZS[15] X Bit 6 R EXZS[14] X Bit 5 R EXZS[13] X Bit 4 R EXZS[12] X Bit 3 R EXZS[11] X Bit 2 R EXZS[10] X Bit 1 R EXZS[9] X Bit 0 R EXZS[8] X EXZS[15:0] In DS3 mode, EXZS[15:0] represents the number of summed Excessive Zeros (EXZS) that occurred during the previous accumulation interval. One or more excessive zeros occurrences within an 85 bit DS3 information block is counted as one summed excessive zero. Excessive zeros are accumulated by this register only when the EXZSO and EXZDET are logic one in the DS3 FRMR Additional Configuration Register. This register accumulates summed LCV when the EXZSO is logic zero. The count of summed LCV is defined as the number of DS3 information blocks (85 bits) that contain one or more LCV since the last time the summed LCV counter was polled. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (314H to 31FH) or to the S/UNI-JET Identification, Master Reset, and Global Monitor Update Register (006H). Such a write transfers the internally accumulated count to the EXZS Event Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK cycles to complete in DS3 mode and a maximum of 500 RCLK cycles to complete in G.832 E3 mode. |
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