C8051F360 datasheet(254/288 Pages) SILABS

254 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

254

Rev. 1.0

SFR Definition 21.3. CKCON: Clock Control

Bit 7:

T3MH: Timer 3 High Byte Clock Select.

This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8-

bit timer mode. T3MH is ignored if Time 3 is in any other mode.

0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.

1: Timer 3 high byte uses the system clock.

Bit 6:

T3ML: Timer 3 Low Byte Clock Select.

This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer

mode, this bit selects the clock supplied to the lower 8-bit timer.

0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.

1: Timer 3 low byte uses the system clock.

Bit 5:

T2MH: Timer 2 High Byte Clock Select.

This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-

bit timer mode. T2MH is ignored if Timer 2 is in any other mode.

0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.

1: Timer 2 high byte uses the system clock.

Bit 4:

T2ML: Timer 2 Low Byte Clock Select.

This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer

mode, this bit selects the clock supplied to the lower 8-bit timer.

0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.

1: Timer 2 low byte uses the system clock.

Bit 3:

T1M: Timer 1 Clock Select.

This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to

logic ‘1’.

0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.

1: Timer 1 uses the system clock.

Bit 2:

T0M: Timer 0 Clock Select.

This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to

logic ‘1’.

0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.

1: Counter/Timer 0 uses the system clock.

Bits 1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.

These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured

to use prescaled clock inputs.

SFR Page:

SFR Address:

all pages

0x8E

R/W

Reset Value

T3MH

T3ML

T2MH

T2ML

T1M

T0M

SCA1

SCA0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SCA1

SCA0

Prescaled Clock

System clock divided by 12

System clock divided by 4

System clock divided by 48

External clock divided by 8

Note: External clock divided by 8 is synchronized with the system clock.

C8051F360 Datasheet(PDF) 254 Page - Silicon Laboratories

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