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XIO2000A Datasheet(PDF) 95 Page - Texas Instruments |
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XIO2000A Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 155 page  Classic PCI Configuration Space 85 April 2007 SCPS155B 4.69 Arbiter Control Register The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration tier. See Table 4−43 for a complete description of the register contents. PCI register offset: DCh Register type: Read/Write Default value: 40h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 1 0 0 0 0 0 0 Table 4−43. Arbiter Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 7† PARK RW Bus parking mode. This bit determines where the internal arbiter parks the secondary bus. When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is cleared, the arbiter parks the bus on the last device mastering the secondary bus. 0 = Park the secondary bus on the last secondary bus master (default) 1 = Park the secondary bus on the bridge 6† BRIDGE_TIER_SEL RW Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 5† TIER_SEL5 RW GNT5 tier select. This bit determines in which tier GNT5 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 4† TIER_SEL4 RW GNT4 tier select. This bit determines in which tier GNT4 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 3† TIER_SEL3 RW GNT3 tier select. This bit determines in which tier GNT3 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 2† TIER_SEL2 RW GNT2 tier select. This bit determines in which tier GNT2 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 1† TIER_SEL1 RW GNT1 tier select. This bit determines in which tier GNT1 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) 0† TIER_SEL0 RW GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) † Thes bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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