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ISD5216PI Datasheet(PDF) 46 Page - Winbond |
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ISD5216PI Datasheet(HTML) 46 Page - Winbond |
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46 / 75 page ![]() ISD5216 - 46 - 1. Connect the microphone to the CODEC input - Bits CDI1 and CDI0 control the state of the CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration Register 0 (CFG0) and they should be set to ONE and ZERO. 2. Power up the ADC—Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2 and it should be a ZERO to power up the ADC. 3. Set the CODEC input gain - The input gain setting will depend on the input level at the MIC+/- pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These are the D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0). 4. Set audio interface - Set the interface mode to PCM-interface by setting bit I 2S0, bit D4 of CFG2, to ZERO. This will also enable full duplex mode. 5. Set data format- Set the digital data format through bits LAW1 and LAW0. These are bits D3 and D2 of CFG2, respectively. 6. Set Master Clock Division - Set the Master Clock division ratios as described in Set Master Clock Division Ratio on page 25. 7. Power up the DAC — Bit DAPD controls the power up state of the DAC. This is bit D1 of CFG2 and should be a ZERO to power up the DAC. 8. Send DAC output to speaker - Select the DAC path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4, respectively, of CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the DAC path. 9. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and AUX amplifiers. These are bits D1 and D2, respectively, of CFG0. They should be set to the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for a higher gain setting (for use with a piezo speaker element) and also powers down the AUX output stage. DAC ADC μ/A-Law Compressor μ/A-Law Expander 2 (LAW1,LAW0) SDI SDIO WS SCK 3 (CIG2,CIG1,CIG0) 3 (COG2,COG1,COG0) MIC+ MIC - INP+ INP- SUM2+ SUM2- Input GAIN SP+ SP- SPEAKER FILTO+ Spkr. AMP (OPA1,OPA0) 2 (OPS1,OPS0) 2 VOL+ SUM2+ DAO+ DAO- SUM2- VOL- FILTO- 2 (LAW1,LAW0) 1 (I2S0) 3 (DAPD,HSR0,MUTE) 4 (ADPD,HSR0,HPF0,MUTE) (CDI1,CDI0) 2 Output GAIN DAC ADC ADC μ/A-Law Compressor μ/A-Law Expander 2 (LAW1,LAW0) 2 (LAW1,LAW0) SDI SDI SDIO SDIO WS WS SCK SCK 3 (CIG2,CIG1,CIG0) 3 (COG2,COG1,COG0) MIC+ MIC - INP+ INP- SUM2+ SUM2- MIC+ MIC - INP+ INP- SUM2+ SUM2- MIC+ MIC - INP+ INP- SUM2+ SUM2- Input GAIN SP+ SP- SPEAKER FILTO+ Spkr. AMP (OPA1,OPA0) 2 (OPS1,OPS0) 2 VOL+ SUM2+ DAO+ DAO- SUM2- VOL- FILTO- 2 (LAW1,LAW0) 2 (LAW1,LAW0) 1 (I2S0) 1 (I2S0) 3 (DAPD,HSR0,MUTE) 4 (ADPD,HSR0,HPF0,MUTE) (CDI1,CDI0) 2 Output GAIN |
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