ISD5216PI datasheet(12/75 Pages) WINBOND

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ISD5216

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The following diagram shows the functional blocks in the CODEC:

7.2.1. Analog Input to Digital Output Path

A 200 kHz anti-aliasing filter processes the analog input signal before entering the amplifier for the

A/D converter. The gain of this amplifier is adjustable through the configuration registers bits (CIG2 –

CIG0) for a gain from 0.80 to 2.00.

The Sigma Delta modulator is a Linear 14 bit

ΣΔ modulator running at a sampling frequency

determined by the external clock input and the internal clock dividers (CKD2, CKDV). The standard

telecom frequency of 8kHz and digital audio of 44.1kHz and 48 kHz as well as intermediate

frequencies as shown in the table on the next page are supported. The A/D converter can be turned

off to save power and reduce noise by setting the A/D power down bit (ADPD).

The A/D converter feeds a 3.4 kHz digital anti aliasing filter which can be muted to suppress noise, the

mute bit controls both the A/D and D/A filter simultaneously. The following high pass filter is enabled

by bit (HPF0) in the configuration register. The High Sampling Rate bit (HSR0) needs to be set to

enable operation at 44.1kHz – 48 kHz.

The digital audio signal can be companded using

μ - Law and A-Law companding or go to the output

uncompressed using 2’s complement or signed magnitude output selected with bits (LAW1 – LAW0)

in the configuration registers.

Finally the digital output interface is selected to be either full-duplex PCM or half duplex I

2S using the

interface selector bit (I

2S0) in the configuration register. The PCM interface uses the SDIO and SDI

pins, the half-duplex I

2S format uses the SDIO pin as both input and output.

ISD5216PI Datasheet(PDF) 12 Page - Winbond