ISD5216PI datasheet(16/75 Pages) WINBOND

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ISD5216

- 16 -

7.3.3. Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable

during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted

as a control signal. The same timing applies to both read and write.

7.3.4. ACKNOWLEDGE

The number of data bytes transferred between the start and stop conditions from transmitter to

receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is

a HIGH level signal put on the interface bus by the transmitter during which time the master generates

an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. In addition, a master receiver must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so

that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-

up and hold times must be taken into consideration). A master receiver must signal an end of data to

the transmitter by not generating an acknowledge on the last byte that has been clocked out of the

slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a

stop condition.

SDA

SCL

data line

stable;

data valid

changed

of data

allowed

Bit transfer on the I

2C-Bus

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

not acknowledge

acknowledge

dock pulse for

acknowledgement

START

condition

Acknowledge on the I

2C-bus

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