ISD5216PI datasheet(48/75 Pages) WINBOND

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ISD5216

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7.10.10. Call Record

The call record mode adds the ability to record the incoming phone call. In most applications, the

ISD5216 would first be set up for Feed Through Mode as described above. When the user wishes to

record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this

explanation, we will use the 6.4 kHz ChipCorder sample rate during recording.

The block diagram of the ISD5216 shows that the Multilevel Storage array is always driven from the

SUM2 SUMMING amplifier. The path traces back from there, through the LOW PASS Filter, the

FILTER MUX, the SUM1 SUMMING amplifier, the SUM1 MUX, back to the origin CODEC. Feed

Through Mode has already powered up the CODEC, so we only need to power up and enable the

path to the Multilevel Storage array from that point:

Setup the feed through mode described in the previous section

Select the CODEC path through the SUM1 MUX

—Bits S1S0 and S1S1 control the state of

the SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to

the state where both D9 and D10 are ZERO to select the CODEC path.

Select the SUM1 MUX input (only) to the S1 SUMMING amplifier

—Bits S1M0 and S1M1

control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of

CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the

SUM1 MUX (only) path.

Select the SUM1 SUMMING amplifier path through the FILTER MUX—

Bit FLS0 controls

the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the

SUM1 SUMMING amplifier path.

Deselect the signal compression

-Bit AMT0 controls the signal compression. This is bit D7

of CFG0 and it must be set to ZERO.

Power up the LOW PASS FILTER

—Bit FLPD controls the power up state of the LOW PASS

FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS

FILTER STAGE.

Select the 6.4 kHz sample rate—

Bits FLD0 and FLD1 select the Low Pass filter setting and

sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To

enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO.

Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—

Bits S2M0 and

S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6,

respectively, of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE

to select the LOW PASS FILTER (only) path.

The configuration settings in the call record mode are:

CFG0=0100 0100 0000 1011 (hex 440B).

CFG1=0000 0000 1100 0101 (hex 00C5).

CFG2=0000 0000 0100 0000 (hex 0040).

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