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TMPR4937 Datasheet(PDF) 478 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 478 Page - Toshiba Semiconductor |
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478 / 552 page  Chapter 15 Interrupt Controller 15-32 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 31 16 Reserved : Type : Default 15 3 2 0 Reserved IML R/W : Type 0 : Default Bit Mnemonic Field Name Explanation Read/Write 31:3 ⎯ ⎯ Reserved ⎯ 2:0 IML Interrupt Mask Level Interrupt Mask Level (Default: 000) These bits specify the interrupt mask level. Masks interrupts with a mask level equal to or lower than the set mask level. 000: Interrupt mask level 0 (No interrupts masked) 001: Interrupt mask level 1 (Levels 2-7 enabled) 010: Interrupt mask level 2 (Levels 3-7 enabled) 011: Interrupt mask level 3 (Levels 4-7 enabled) 100: Interrupt mask level 4 (Levels 5-7 enabled) 101: Interrupt mask level 5 (Levels 6-7 enabled) 110: Interrupt mask level 6 (Level 7 enabled) 111: Interrupt mask level 7 (Interrupts disabled) R/W Figure 15.4.12 Interrupt Mask Register |
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