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TMPR4937 Datasheet(PDF) 479 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 479 Page - Toshiba Semiconductor

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Chapter 15 Interrupt Controller
15-33
15.4.13 Interrupt Edge Detection Clear Register (IREDC)
0xF660
31
16
Reserved
: Type
: Default
15
9
8
7
4
3
0
Reserved
EDCE0
Reserved
EDCS0
RW1C
R/W
: Type
0
0000
: Default
Bit
Mnemonic
Field Name
Explanation
Read/Write
31:9
⎯
⎯
Reserved
⎯
8
EDCE0
Edge Detection
Clear Enable 0
Edge Detection Clear Enable 0 (Default: 0)
Clears edge detection of interrupts specified by the EDCS0 field.
0: Does not clear.
1: Clears.
Value always becomes “0” when this bit is read.
R/W1C
7:4
⎯
⎯
Reserved
⎯
3:0
EDCS0
Edge Detection
Clear Source 0
Edge Detection Clear Source 0 (Default: 0x0)
These bits specify the interrupt source to be cleared.
1111: Reserved
1110: Reserved
1101: Reserved
1100: Reserved
1011: Reserved
1010: Reserved
1001: Reserved
1000: Reserved
0111: External INT [5] interrupt
0110: External INT [4] interrupt
0101: External INT [3] interrupt
0100: External INT [2] interrupt
0011: External INT [1] interrupt
0010: External INT [0] interrupt
0001: Reserved
0000: Reserved
R/W
Figure 15.4.13 Interrupt Status Control Register



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